IP Library Granted Patent US 7,633,111
Granted Patent B2
US 7,633,111 · App. 11/197,358 · Granted Dec 15, 2009

Semiconductor structure

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Quick Facts
Patent No.
US 7,633,111
App. No.
11/197,358
Granted
Dec 15, 2009
Kind
B2
Abstract

A semiconductor structure, for improving rectifier efficiency in passive backscatter transponders or backscatter remote sensors for use in high-frequency electromagnetic fields, is provided. The semiconductor structure has a dielectric layer on whose upper side is arranged a first electrically conductive layer, and a second electrically conductive layer that is spaced apart from the first electrically conductive layer and is arranged essentially below the first electrically conductive layer and is at least partially embedded in the dielectric layer. The dielectric layer has its lower side arranged on a semiconductor substrate of a first conductivity type within which is formed a more highly doped first zone of the first conductivity type which surrounds an even more highly doped second zone of the first conductivity type connected to a reference voltage. Whereby, the first zone can be arranged essentially completely under the first and second electrically conductive layers. In this way, interfering effects of parasitic circuit components can be reduced.

Claims (32)

1. A semiconductor structure comprising:

a dielectric layer;

a first electrically conductive layer being provided on an upper side of the dielectric layer; and

a second electrically conductive layer that is spaced apart from the first electrically conductive layer and is arranged below the first electrically conductive layer and is at least partially embedded in the dielectric layer,

wherein the dielectric layer has a portion of a lower side thereof provided on a semiconductor substrate that has a first conductivity type,

wherein there is formed within the semiconductor substrate a highly doped first zone of the first conductivity type, the first zone partially encompassing a greater doped second zone having the first conductivity type, the second zone being connected to a reference voltage, and

wherein the entirety of the first zone is arranged under the first and second electrically conductive layers.

2. The semiconductor structure according to claim 1 , wherein a capacitor, which is formed by the first and second electrically conductive layers, is connected by the first electrically conductive layer to a subsequent stage of a multistage rectifier circuit and is connected by the second electrically conductive layer to a first stage of the multistage rectifier circuit.

3. The semiconductor structure according to claim 1 , wherein the first electrically conductive layer is formed by a receiving device of the semiconductor structure for receiving electromagnetic waves.

4. The semiconductor structure according to claim , wherein the first and second electrically conductive layers have a substantially horizontal plane and are parallel to one another.

5. The semiconductor structure according to claim 1 , further comprising at least one first layer having metallic properties is arranged in a junction region between the dielectric layer and the first zone and below the second electrically conductive layer, the at least one first layer being electrically connected to the second electrically conductive layer.

6. The semiconductor structure according to claim 1 , wherein the second electrically conductive layer has metallic properties and extends, at least in sections, into a junction region that is formed between the dielectric layer and the first zone that is below the second electrically conductive layer.

7. The semiconductor structure according to claim 1 , wherein there is formed in the semiconductor substrate a more highly doped third zone having a second conductivity type, the third zone partially surrounding an even more highly doped fourth zone having the second conductivity type, the fourth being connected to a reference voltage, and wherein the third zone is arranged under the first and second electrically conductive layers.

8. The semiconductor structure according to claim 7 , wherein at least one second layer having metallic properties is arranged in a junction region between the dielectric layer and the third zone that is below the second electrically conductive layer, the at least one second layer being electrically connected to the second electrically conductive layer.

9. The semiconductor structure according to claim 7 , wherein the second electrically conductive layer has metallic properties and extends, at least in sections, into a junction region formed between the dielectric layer and the third zone that is below the second electrically conductive layer.

10. The semiconductor structure according to one claim 1 , wherein, on the first electrically conductive layer, a deposit is formed of an electrically conductive material which projects above the upper side of the dielectric layer.

11. The semiconductor substrate according to claim 1 , wherein the semiconductor substrate is provided in a power supply circuit for an integrated circuit, a backscatter transponder, or a remote sensor.

12. The semiconductor substrate according to claim 1 , wherein the semiconductor substrate is provided in a circuit for detecting a strength of a received signal in a backscatter transponder or a remote sensor.

13. The semiconductor structure according to claim 1 , wherein the semiconductor structure increases rectifier efficiency in passive backscatter transponders or backscatter remote sensors that are used in high-frequency electromagnetic fields.

14. The semiconductor structure according to claim 2 , wherein the receiving device is an antenna of a transponder or remote sensor.

15. A transponder comprising:

a semiconductor substrate having a first conductivity type;

a dielectric layer, the dielectric layer having a lower surface adjacent to a portion of an upper surface of the semiconductor substrate;

a first electrically conductive layer being provided on an upper surface of the dielectric layer;

a second electrically conductive layer being provided in a portion of the dielectric layer such that the second electrically conductive layer is between the first electrically conductive layer and the semiconductor substrate, the second electrically conductive layer having first and second opposite edges;

a doped first zone of the first conductivity type being partially formed within the semiconductor substrate and projecting under said first and second opposite edges of the second electrically conductive layer; and

a doped second zone of the first conductivity type, the doped second zone being partially encompassed by the doped first zone, the doped second zone having a higher doping than the doped first zone.

16. The transponder according to claim 15 , wherein the transponder is a passive transponder.

17. The transponder according to claim 15 , wherein the second electrically conductive layer is provided between the doped first zone and the first electrically conductive layer.

18. The transponder according to claim 15 , wherein a portion of an upper surface of the doped first zone contacts a portion of a lower surface of the second electrically conductive layer.

19. The transponder according to claim 15 , wherein the first electrically conductive layer and the second electrically conductive layer are substantially parallel.

20. The transponder according to claim 15 , wherein the first electrically conductive layer and the second electrically conductive layer are electrically connected to a rectifier circuit or a multi-stage rectifier circuit.

Assignments (19)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Apr 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: ATMEL CORPORATION
Reel/Frame 038376/0001 →
PATENT SECURITY AGREEMENT Recorded Jan 3, 2014
From: ATMEL CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC. AS ADMINISTRATIVE AGENT
Reel/Frame 031912/0173 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 4, 2011
From: ATMEL AUTOMOTIVE GMBH
To: ATMEL CORPORATION
Reel/Frame 025899/0710 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 9, 2009
From: ATMEL GERMANY GMBH
To: ATMEL AUTOMOTIVE GMBH
Reel/Frame 023205/0838 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 22, 2005
From: ULRICH FRIEDRICH
To: ATMEL GERMANY GMBH
Reel/Frame 017010/0271 →