Method for manufacturing wafer level chip scale package using redistribution substrate
The present invention provides a method for manufacturing a wafer level chip scale package using a redistribution substrate, which has patterned bump pairs connected by redistribution lines and formed on a transparent insulating substrate. The redistribution substrate is produced separately from a wafer and then bonded to the wafer. One part of each bump pair is in contact with a chip pad on the active surface of the wafer, and the other part coincides with one of holes formed in the wafer. Conductive lines are formed in the holes and on the non-active surface of the wafer. External connection terminals are formed on the conductive lines at the non-active surface.
1. A method for manufacturing a wafer level chip scale package, the method comprising:
(a) producing a redistribution substrate having a transparent insulating substrate and redistribution lines formed on the transparent insulating substrate;
(b) providing a wafer having a semiconductor substrate having an active surface and at least one non-active surface, the wafer further having chip pads formed on the active surface;
(c) bonding the redistribution substrate to the wafer so that first parts of the redistribution lines are connected with the chip pads;
(d) forming holes extended from the active surface to the non-active surface in the wafer so that the second parts of the redistribution lines are exposed to the holes;
(e) forming conductive lines in the holes and on the non-active surface;
(f) forming external connection terminals on the conductive lines formed on the non-active surface; and
(g) dividing both the redistribution substrate and the wafer along a scribe line.
2. The method of claim 1 , wherein the (a) step includes:
(a-1) providing the transparent insulating substrate;
(a-2) providing an insulating layer on the transparent insulating substrate;
(a-3) forming bumps by patterning the insulating layer; and
(a-4) forming the redistribution lines on the bumps.
3. The method of claim 1 , wherein the transparent insulating substrate is made of glass, quartz, or acrylic resin.
4. The method of claim 2 , wherein the (a-3) step further includes forming dams by patterning the insulating layer.
5. The method of claim 2 , wherein the (a-3) step is forming pairs of bumps, each pair having a first bump connected with the chip pad and a second bump exposed to the hole.
6. The method of claim 2 , wherein the insulating layer is made of polymer.
7. The method of claim 1 , wherein the redistribution lines are made of materials selected from the group including copper (Cu), nickel (Ni), titanium (Ti), chromium (Cr), tungsten (W), or their compositions.
8. The method of claim 2 , wherein the (a-4) step is implemented using techniques selected from the group including sputtering, electroplating, deposition, electroless plating, screen printing, or ink printing.
9. The method of claim 1 , wherein the wafer further has an image sensing area formed on the active surface.
10. The method of claim 1 , wherein the wafer further has at least one pad metal layer formed on the chip pads.
11. The method of claim 10 , wherein the pad metal layer is made of materials selected form the group including gold (Au), nickel (Ni), aluminum (Al), copper (Cu), tin (Sn), or their compositions.
12. The method of claim 1 , wherein the bonding between the redistribution substrate and the wafer in the (c) step is established using a photosensitive adhesive.
13. The method of claim 1 , wherein the connection between the redistribution lines and the chip pads in the (c) step is made using an indium (In)-based adhesive.
14. The method of claim 1 , wherein the bonding between the redistribution substrate and the wafer in the (c) step is made using anisotropic conductive material or nano interconnection paste.
15. The method of claim 1 , further comprising:
after the (c) step, mechanically grinding a bottom surface of the wafer so as to reduce the thickness of the wafer.
16. The method of claim 15 , wherein the wafer is thinned down to the thickness of about 50˜150 μm by the grinding step.
17. The method of claim 1 , wherein the (d) step is implemented using techniques selected from the group including laser drilling, mechanical drilling, plasma dry etching, or reactive ion etching.
18. The method of claim 1 , wherein the (e) step includes forming at least one conductive layer in the holes and on the non-active surface, and selectively removing the conductive layer so as to create the conductive lines.
19. The method of claim 1 , wherein the (e) step includes forming a photoresist pattern corresponding to the conductive lines on the non-active surface, and performing a selective electroplating through the photoresist pattern so as to create the conductive lines.
20. The method of claim 1 , wherein the conductive lines has first conductive lines and second conductive lines formed on the first conductive lines.
21. The method of claim 20 , wherein the first conductive lines are formed of materials selected from the group including tungsten (W), titanium (Ti), aluminum (Al), zirconium (Zr), chromium (Cr), copper (Cu), gold (Au), silver (Ag), lead (Pb), nickel (Ni), indium tin oxide (ITO), or their compositions.
22. The method of claim 20 , wherein the second conductive lines are formed of one composition selected from the group including chromium (Cr), titanium (Ti), tungsten (W), copper (Cu), nickel (Ni), gold (Au), and titanium tungsten (TiW).
23. The method of claim 1 , further comprising:
after the (e) step, forming a dielectric protective layer on the conductive lines so as to protect the conductive lines and to define terminal locations.
24. The method of claim 1 , wherein the external connection terminals in the (f) step are formed on a bottom surface of the semiconductor substrate, or otherwise on at least one lateral side surface of the semiconductor substrate.