IP Library Granted Patent US 7,501,697
Granted Patent B2
US 7,501,697 · App. 11/276,946 · Granted Mar 10, 2009

Integrated circuit package system

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Quick Facts
Patent No.
US 7,501,697
App. No.
11/276,946
Granted
Mar 10, 2009
Kind
B2
Abstract

An integrated circuit package system is provided forming a carrier having a top side and a bottom side, forming an edge terminal pad on the top side and an inner terminal pad on the bottom side, connecting an integrated circuit die to an inner portion of the edge terminal pad, and encapsulating the integrated circuit die and the inner portion of the edge terminal pad with the outer portion of the edge terminal pad exposed.

Claims (40)

1. An integrated circuit package system comprising:

forming a carrier having a top side and a bottom side;

forming an edge terminal pad on the top side and an inner terminal pad on the bottom side;

connecting an integrated circuit die to an inner portion of the edge terminal pad;

encapsulating the integrated circuit die and the inner portion of the edge terminal pad with the outer portion of the edge terminal pad exposed and forming an interposer having a boundary terminal pad and an interior terminal pad;

mounting the interposer on the integrated circuit die;

connecting the boundary terminal pad to the inner portion of the edge terminal pad; and

encapsulating the interposer with the interior terminal pad exposed.

2. An integrated circuit package system comprising:

forming a carrier having a top side and a bottom side;

forming a bond finger on the top side at the boundary of the top side;

forming an inner terminal pad in a central portion on the the bottom side;

mounting an integrated circuit die to the top side;

connecting the integrated circuit die to an inner portion of the bond finger;

encapsulating the integrated circuit die and the inner portion of the bond finger with the outer portion of the bond finger exposed and forming an interposer having a boundary terminal pad and an interior terminal pad;

mounting the interposer on the integrated circuit die;

connecting the boundary terminal pad to the inner portion of the edge terminal pad; and

encapsulating the interposer with the interior terminal pad exposed.

3. The system as claimed in claim 2 further comprising forming an array of inner terminal pads in the central portion on the bottom side.

4. The system as claimed in claim 2 further comprising attaching an external interconnect to the inner terminal pad.

5. An integrated circuit package system comprising:

a carrier having a top side and a bottom side;

an edge terminal pad on the top side and an inner terminal pad on the bottom side;

an integrated circuit die connected to an inner portion of the edge terminal pad;

a first encapsulation to cover the integrated circuit die and the inner portion of the edge terminal pad with the outer portion of the edge terminal pad exposed and an interposer having a boundary terminal pad and an interior terminal pad;

the interposer being on the integrated circuit die;

the boundary terminal pad connected to the inner portion of the edge terminal pad; and

the first encapsulation to cover the interposer with the interior terminal pad exposed.

6. The system as claimed in claim 5 wherein:

the carrier having the top side and the bottom side has a bond site;

the edge terminal pad on the top side is a bond finger and the inner terminal pad on the bottom side is in a central portion of the bottom side;

the integrated circuit die connected to the inner portion of the edge terminal pad is mounted on the top side; and

the first encapsulation to cover the integrated circuit die and the inner portion of the edge terminal pad with the outer portion of the edge terminal pad exposed.

7. The system as claimed in claim 6 further comprising an external interconnect attached to the inner terminal pad.

8. The system as claimed in claim 6 further comprising an array of inner terminal pads in the central portion on the bottom side.

9. The system as claimed in claim 6 further comprising:

an interposer having a boundary terminal pad and an array of interior terminal pads;

the interposer on the integrated circuit die;

the boundary terminal pad connected to the inner portion of the bond finger; and

the first encapsulation to cover the interposer with the interior terminal pads exposed.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECT ERROR IN ASSIGNMENT NAME FROM STATS CHIPPAC, PTE. LTE TO STATS CHIPPAC PTE. LTD (REEL: 038378 FRAME: 0319) Recorded Aug 30, 2023
From: STATS CHIPPAC PTE. LTE.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064760/0986 →
RELEASE OF SECURITY INTEREST Recorded Jun 15, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052938/0305 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0319 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Mar 18, 2006
From: YIM, CHOONG BIN; KWON, HYEOG CHAN; HA, JONG-WOO
To: STATS CHIPPAC LTD.
Reel/Frame 017330/0717 →