Integrated circuit package system with net spacer

1. A method for manufacturing an integrated circuit package system comprising:

forming a strip level net spacer including support bars, tie bars and paddles;

configuring the support bars, the tie bars and the paddles to form four or more open regions around each of the paddles, the support bars bounding less than all of the open regions; and

interconnecting the support bars, the tie bars and the paddles to provide structural support to vertically stacked semiconductor devices formed above first semiconductor device and directly attached to the paddles.

2. The method as claimed in claim 1 further comprising:

providing an adhesive layer of the bottom of the paddles.

3. The method as claimed in claim 1 wherein:

interconnecting the support bars, the tie bars and the paddles provides structural support to second semiconductor devices formed over first semiconductor devices during attachment and wire bonding.

4. The method as claimed in claim 1 wherein:

forming the strip level net spacer includes forming the strip level net spacer of plastic or heat dissipating material.

5. The method as claimed in claim 1 further comprising:

configuring the strip level net spacer to prevent warping of a substrate.

6. A method for manufacturing an integrated circuit package system comprising:

providing a substrate with first semiconductor devices interconnected to the substrate;

forming over the substrate a strip level net spacer including paddles used for supporting second semiconductor devices and tie bars which interconnect the paddles to support bars wherein the paddles, the tie bars, and the support bars are configured to form four or more open regions around each of the paddles with the support bars bonding less than all of the open regions; and

stacking the second semiconductor devices over the first semiconductor devices, the second semiconductor devices directly attached to the paddles.

7. The method as claimed in claim 6 further comprising:

interconnecting the first semiconductor devices and the second semiconductor devices to the substrate via with bonding.

8. The method as claimed in claim 6 further comprising:

providing an adhesive layer in the bottom of the paddles for bonding to the first semiconductor device.

9. The method as claimed in claim 6 wherein:

providing the substrate with the first semiconductor devices includes quad-flat non-leaded packages, wire bond packages, single and dual-side memory packages, internal stacking module packages, flip-chip packages, modular packages, application-specific-integrated-circuit (ASIC) packages, stacked die packages, wire bond die, flip-chip die, stacked die, modular die, ASIC die, passive devices or a combination thereof.

10. The method as claimed in claim 6 wherein:

providing the second semiconductor devices includes quad-flat non-leaded packages, wire bond packages, single and dual-side memory packages, internal stacking module packages, flip-chip packages, modular packages, application-specific-integrated-circuit (ASIC) packages, stacked die packages, wire bond die, flip-chip die, stacked die modular die, ASIC die, passive devices or a combination thereof.

11. An integrated circuit package system comprising:

a substrate with a first semiconductor device interconnected to the substrate;

a strip level net spacer including a paddle and tie bars which interconnect the paddle to support bars, wherein the paddle, the tie bars, and the support bars are configured to form four or more open regions around the paddle with the su ort bars bounding less than all of the open regions; and

a second semiconductor device over the first semiconductor device and directly attached to the paddle.

12. The system as claimed in claim 11 further comprising:

an adhesive layer on the bottom of the paddle.

13. The system as claimed in claim 11 wherein:

the support bars, the tie bars and the paddle provide structural support to the second semiconductor device that prevents delamination and chip cracking.

14. The system as claimed in claim 11 wherein:

the strip level net spacer is formed of plastic or heat dissipating material.

15. The system as claimed in claim 11 wherein:

the strip level net spacer prevents warping of a substrate.

16. The system as claimed in claim 11 further comprising:

the first semiconductor device and the second semiconductor device interconnected to the substrate via wire bonding.

17. The system as claimed in claim 16 wherein:

the first semiconductor device includes quad-flat non-leaded packages, wire bond packages, single and dual-side memory packages, internal stacking module packages, flip-chip packages, modular packages, application-specific-integrated-circuit (ASIC) packages, stacked die packages, wire bond die, flip-chip die, stacked die modular die, ASIC die, passive devices or a combination thereof.

18. The system as claimed in claim 16 wherein:

the second semiconductor device includes quad-flat non-leaded packages, wire bond packages, single and dual-side memory packages, internal stacking module packages, flip-chip packages, modular packages, application-specific-integrated-circuit (ASIC) packages, stacked die packages, wire bond die, flip-chip die, stacked die, modular die, ASIC die, passive devices or a combination thereof.

19. The system as claimed in claim 16 wherein:

the strip level net spacer includes a plurality of the paddles;

the substrate includes a plurality of the first semiconductor devices; and

the integrated circuit package system includes a plurality of the second semiconductor devices.

20. The system as claimed in claim 16 further comprising:

an adhesive layer on the bottom of the paddle for bonding to the first semiconductor device.