Granted Patent B2

US 7,710,735 · App. 11/278,418 · Granted May 4, 2010

Abstract

Claims (78)

1. A multichip integrated circuit package system comprising:

providing a substrate having a substrate top surface and a substrate bottom surface;

attaching a first integrated circuit die on the substrate top surface;

encapsulating the first integrated circuit die in a first encapsulation;

mounting a second integrated circuit die over the first integrated circuit die;

attaching an interconnect to the substrate bottom surface and the second integrated circuit die;

connecting an external interconnect on the substrate bottom surface; and

forming a second encapsulation over the interconnect and having a recess to expose a portion of the substrate bottom surface and the external interconnect.

2. The system as claimed in claim 1 wherein:

attaching the first integrated circuit die on the substrate top surface comprises:

electrically connecting the first integrated circuit die and the substrate top surface; and

further comprising:

electrically connecting the second integrated circuit die and the substrate bottom surface.

3. The system as claimed in claim 1 further comprising:

electrically connecting the first integrated circuit die and the substrate bottom surface; and

electrically connecting the first integrated circuit die and the second integrated circuit die.

4. The system as claimed in claim 1 further comprising: forming a second substrate having an opening, the second substrate having a second substrate top surface and a second substrate bottom surface; and electrically connecting the first integrated circuit die and the second substrate bottom surface through the opening.

5. The system as claimed in claim 1 further comprising: electrically connecting the first integrated circuit die and the substrate bottom surface; and electrically connecting the first integrated circuit die and the second integrated circuit die.

6. A multichip integrated circuit package system comprising:

providing a substrate having a substrate top surface and a substrate bottom surface;

attaching a first integrated circuit die on the substrate top surface, having a first conductive trace;

encapsulating the first integrated circuit die in the first encapsulation;

mounting a second integrated circuit die over the first integrated circuit die with an adhesive on an active side of the second integrated circuit die;

attaching an interconnect to the substrate bottom surface and the second integrated circuit die;

connecting an external interconnect on the substrate bottom surface, having a second conductive trace; and

forming a second encapsulation over the interconnect and having a recess to expose a portion of the substrate bottom surface and the external interconnect as well as covering the substrate top surface.

7. The system as claimed in claim 6 wherein:

attaching the first integrated circuit die on the substrate top surface comprises:

electrically connecting the first integrated circuit die and a first peripheral portion of the substrate top surface; and

further comprising:

partially encapsulating the second integrated circuit die; and

electrically connecting the second integrated circuit die and a second peripheral portion of the substrate bottom surface.

8. The system as claimed in claim 6 further comprising:

electrically connecting the first integrated circuit die and a peripheral portion of the substrate bottom surface;

electrically connecting the first integrated circuit die and the second integrated circuit die; and

partially encapsulating the second integrated circuit die.

9. The system as claimed in claim 6 further comprising: forming a second substrate having an opening, the second substrate having a second substrate top surface and a second substrate bottom surface; electrically connecting the first integrated circuit die and a flexible lead on the second substrate bottom surface through the opening.

10. The system as claimed in claim 6 further comprising: electrically connecting the first integrated circuit die and a flexible lead of the substrate bottom surface; and electrically connecting the first integrated circuit die and the second integrated circuit die.

11. A multichip integrated circuit package system comprising:

a substrate having a substrate top surface and a substrate bottom surface;

a first integrated circuit die on the substrate top surface;

a first encapsulation over the first integrated circuit die;

a second integrated circuit die over the first integrated circuit die;

an interconnect attached to the substrate bottom surface and the second integrated circuit die;

an external interconnect on the substrate bottom surface; and

a second encapsulation over the interconnect and having a recess to expose a portion of the substrate bottom surface and the external interconnect.

12. The system as claimed in claim 11 wherein:

the first integrated circuit die on the substrate top surface comprises:

a first interconnect between the first integrated circuit die and the substrate top surface; and

further comprising:

a second interconnect between the second integrated circuit die and the substrate bottom surface.

13. The system as claimed in claim 11 further comprising:

a first interconnect between the first integrated circuit die and the substrate bottom surface; and

a second interconnect between the first integrated circuit die and the second integrated circuit die.

14. The system as claimed in claim 11 further comprising: a second substrate having an opening, the second substrate having a second substrate top surface and a second substrate bottom surface; and an interconnect between the first integrated circuit die and the second substrate bottom surface through the opening.

15. The system as claimed in claim 11 further comprising:

a first interconnect between the first integrated circuit die and the substrate bottom surface;

a second interconnect between the first integrated circuit die and the second integrated circuit die; and

the second encapsulation to cover the first integrated circuit die and the second integrated circuit die.

16. The system as claimed in claim 11 wherein:

the first integrated circuit die is on the substrate top surface, the substrate top surface having a first conductive trace;

the second integrated circuit die is over the first integrated circuit die with an adhesive on an active side of the second integrated circuit die;

the external interconnect is on the substrate bottom surface, the substrate bottom surface having a second conductive trace; and

the second encapsulation covers the substrate top surface.

17. The system as claimed in claim 16 wherein:

the first integrated circuit die on the substrate top surface comprises:

a first interconnect is between the first integrated circuit die and a first peripheral portion of the substrate top surface; and

further comprising:

the second encapsulation partially covers the second integrated die; and

a second interconnect between the second integrated circuit die and a second peripheral portion of the substrate bottom surface.

18. The system as claimed in claim 16 further comprising:

a first interconnect between the first integrated circuit die and a peripheral portion of the substrate bottom surface;

a second interconnect between the first integrated circuit die and the second integrated circuit die; and

the second encapsulation partially covers the second integrated circuit die.

19. The system as claimed in claim 16 further comprising: a second substrate having an opening, the second substrate having a second substrate top surface and a second substrate bottom surface; and a first interconnect between the first integrated circuit die and a flexible lead on the second substrate bottom surface through the opening.

20. The system as claimed in claim 16 further comprising:

a first interconnect between the first integrated circuit die and a flexible lead of the substrate bottom surface; and

a second interconnect between the first integrated circuit die and the second integrated circuit die.

Assignments (6)