Semiconductor device and method for manufacturing the same
View Patent ↗A semiconductor device and a method for manufacturing the same are disclosed, in which an insulating layer may be formed in a strained silicon layer under source/drain regions to substantially overcome conventional problems resulting from a channel decrease in the semiconductor device. A method for manufacturing the semiconductor device may include growing a germanium layer on a first silicon layer; forming at least two trenches in the germanium layer; forming an insulating layer in the germanium layer including the trenches; forming at least two gate insulating layer patterns by polishing the germanium layer and the insulating layer to coplanarity in the bottom of the trenches; re-growing and planarizing the germanium layer; forming a second silicon layer on the germanium layer; forming a gate insulating layer and a gate electrode on the second silicon layer between the at least two insulating layers; and forming source/drain regions by implanting impurity ions into the second silicon layer at sides of the gate electrode.
1. A method for manufacturing a semiconductor device, comprising the steps of:
growing a germanium layer on a first silicon layer;
forming at least two trenches in the germanium layer;
forming an insulating layer in the germanium layer including the trenches;
forming at least two insulating layer portions by polishing the germanium layer and the insulating layer to coplanarity at the bottom of the trenches;
re-growing and planarizing the germanium layer;
forming a second silicon layer on the germanium layer;
forming a gate insulating layer and a gate electrode on the second silicon layer between the at least two insulating layer portions; and
forming source/drain regions by implanting impurity ions into the second silicon layer at sides of the gate electrode.
2. The method of claim 1 , wherein silicon (Si 1-x ) and germanium (Ge x ) are present in a composition ratio such that x is from about 0.1 to about 0.5.
3. The method of claim 1 , wherein the at least two insulating layer patterns extend at least to a depletion point of the source/drain regions.
4. The method of claim 1 , wherein the second silicon layer has a thickness of from about 50 Å to about 250 Å.
5. The method of claim 1 , wherein the gate electrode overlaps with the at least two gate insulating layer portions.
6. A method for manufacturing a semiconductor device, comprising the steps of:
forming at least two insulating layer portions on or in a first germanium layer on a first silicon layer;
growing a second germanium layer on the polished germanium layer and planarizing the second germanium layer;
forming a second silicon layer on the germanium layer;
forming a gate insulating layer and a gate electrode on the second silicon layer between the at least two insulating layer portions; and
forming source/drain regions by implanting impurity ions into the second silicon layer at opposed sides of the gate electrode.
7. The method of claim 6 , wherein the gate electrode overlaps with the at least two gate insulating layer portions, and the at least two gate insulating layer portions are formed such that a portion of the first germanium layer is between the at least two gate insulating layer portions.