IP Library Patent Application 11307498
Patent Application
App. No. 11/307,498

STACKED INTEGRATED CIRCUITS PACKAGE SYSTEM

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Quick Facts
Patent No.
US None
App. No.
11/307,498
Abstract

A stacked integrated circuits package system is provided providing a first substrate, mounting a first integrated circuit having a recess to the first substrate, and mounting a second integrated circuit in the recess.

Claims (51)

1 . A stacked integrated circuits package system comprising:

providing a first substrate;

mounting a first integrated circuit having a recess to the first substrate; and

mounting a second integrated circuit in the recess.

2 . The system as claimed in claim 1 wherein mounting the first integrated circuit having a recess to the first substrate comprises etching the recess on a back side of the first integrated circuit.

3 . The system as claimed in claim 1 further comprising locally thinning a back side of the first integrated circuit.

4 . The system as claimed in claim 1 further comprising:

attaching electrical interconnect structures on the second integrated circuit;

connecting a second substrate to the electrical interconnect structures on the second integrated circuit; and

electrically connecting the second substrate to the first substrate.

5 . The system as claimed in claim 1 wherein mounting a second integrated circuit in the recess comprises:

mounting a second substrate in the recess;

forming electrical interconnect structures to the second integrated circuit;

connecting the electrical inteconnect structures on the second integrated circuit to the second substrate;

mounting a third integrated circuit on the second integrated circuit; and

electrically connecting the second substrate and the third integrated circuit to the first substrate.

6 . A stacked integrated circuits package system comprising:

providing a first substrate;

providing a first integrated circuit having electrical interconnect structures on an active side;

mounting the first integrated circuit on the first substrate with the electrical interconnect structures;

etching a recess on the back side of the first integrated circuit;

attaching a second integrated circuit in the recess; and

electrically connecting the second integrated circuit to the first substrate.

7 . The system as claimed in claim 6 further comprising encapsulating a mold compound over the first integrated circuit, the second integrated circuit, and the first substrate.

8 . The system as claimed in claim 6 wherein electrically connecting the second integrated circuit comprises connecting wire bonds to electrically connect the second integrated circuit to the first substrate.

9 . The system as claimed in claim 6 further comprising forming solder bumps on the first integrated circuit to electrically connect the first integrated circuit to the first substrate.

10 . The system as claimed in claim 6 further comprising etching the back side of the first integrated circuit.

11 . A stacked integrated circuits package system comprising:

a first substrate having a first integrated circuit mounted thereto;

a recess in the first integrated circuit; and

a second integrated circuit in the recess.

12 . The system as claimed in claim 11 wherein the recess in the first integrated circuit comprises the recess on a back side of the first integrated circuit.

13 . The system as claimed in claim 11 wherein the first integrated circuit having the recess includes the recess having different geometric shapes.

14 . The system as claimed in claim 11 further comprising:

electrical interconnect structures on the second integrated circuit;

a second substrate connected to the electrical interconnect structures on the second integrated circuit; and

the second substrate electrically connected to the first substrate.

15 . The system as claimed in claim 11 wherein the second integrated circuit in the recess comprises:

a second substrate in the recess;

electrical interconnect structures on the second integrated circuit, wherein the electrical interconnect structures electrically connected on the second substrate;

a third integrated circuit on the second integrate circuit; and

the second substrate and the third integrated circuit electrically connected to the first substrate.

16 . A stacked integrated circuits package system comprising:

a first substrate;

a first integrated circuit having electrical interconnect structures on an active side, wherein the first integrated circuit mounted on the first substrate with the electrical interconnect structures;

a recess on the back side of the first integrated circuit;

a second integrated circuit in the recess, wherein the second integrated circuit electrically connected to the first substrate.

17 . The system as claimed in claim 16 further comprising a mold compound over the first integrated circuit, the second integrated circuit, and the first substrate.

18 . The system as claimed in claim 16 further comprising wire bonds to electrically connect the second integrated circuit to the first substrate.

19 . The system as claimed in claim 16 further comprising solder bumps on the first integrated circuit to electrically connect the first integrated circuit to the first substrate.

20 . The system as claimed in claim 16 further comprising integrated circuits stacked above the second integrated circuit electrically connected to the first substrate.

Assignments (6)
RELEASE OF SECURITY INTEREST Recorded Jun 17, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 053476/0094 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR NAME PREVIOUSLY RECORDED AT REEL: 039514 FRAME: 0451. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Aug 26, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 039980/0838 →
CORRECTIVE ASSIGNMENT TO CORRECT THE ASSIGNOR'S NAME PREVIOUSLY RECORDED ON REEL 038378 FRAME 0442. ASSIGNOR(S) HEREBY CONFIRMS THE CHANGE OF NAME. Recorded Jul 26, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 039514/0451 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0442 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 9, 2006
From: PARK, SEUNG WOOK; BAE, SOON HEUNG
To: STATS CHIPPAC LTD.
Reel/Frame 017149/0767 →