IP Library Granted Patent US 7,617,427
Granted Patent B2
US 7,617,427 · App. 11/324,084 · Granted Nov 10, 2009

Method and apparatus for detecting defects in integrated circuit die from stimulation of statistical outlier signatures

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Quick Facts
Patent No.
US 7,617,427
App. No.
11/324,084
Granted
Nov 10, 2009
Kind
B2
Abstract

A method and computer program for detecting and locating defects in integrated circuit die from stimulation of statistical outlier signatures includes receiving as input a test value of an electrical parameter measured for each of a plurality of identically designed electrical circuits, identifying one of the identically designed electrical circuits as an outlier for which the test value of the electrical parameter varies from a mean test value of the electrical parameter for the plurality of identically designed electrical circuits by at least a selected difference, monitoring the test value while subjecting a location on the outlier to a stimulus to detect a change in the test value as a function of the location, and generating as output the location for which the change in the test value is detected to identify a defect in the outlier.

Claims (34)

1. A method comprising steps of:

(a) receiving as input a test value of an electrical parameter measured for each of a plurality of identically designed electrical circuits;

(b) identifying one of the identically designed electrical circuits as an outlier for which the test value of the electrical parameter varies from a mean test value of the electrical parameter for the plurality of identically designed electrical circuits by at least a selected difference;

(c) monitoring the test value while subjecting a location on the outlier to a stimulus to detect a change in the test value as a function of the location; and

(d) generating as output the location for which the change in the test value is detected to identify a defect in the outlier;

wherein each of steps (a), (b), (c) and (d) is performed by one or more computers.

2. The method of claim 1 wherein step (c) comprises subjecting the outlier to a beam of at least one of optical radiation, thermal radiation, and charged particles.

3. The method of claim 1 wherein step (a) comprises measuring an electrical parameter comprising at least one of minimum operating voltage, maximum operating voltage, minimum operating frequency, maximum operating frequency, static leakage current, and dynamic leakage current.

4. The method of claim 3 comprising measuring the electrical parameter as a function of at least one of a test vector, a clock cycle, a supply voltage, and a device logic state.

5. The method of claim 1 comprising calculating the selected difference as a multiple of a standard deviation of the electrical parameter for the plurality of identically designed electrical circuits.

6. The method of claim 1 wherein step (c) comprises applying the stimulus to one of a plurality of scanned coordinates on the outlier.

7. The method of claim 1 wherein step (c) comprises applying the stimulus to successively smaller areas on the outlier.

8. The method of claim 1 wherein step (a) comprises measuring the electrical parameter for each of a plurality of identically designed electrical circuits having no stuck-at faults.

9. The method of claim 1 wherein step (a) comprises measuring the electrical parameter for each of a plurality of identically designed electrical circuits having no transition delay faults.

10. The method of claim 1 wherein step (a) comprises measuring a test value of an electrical parameter that does not include operating current.

11. A computer program product comprising: a computer usable storage medium having computer usable program code embodied therewith, the computer usable program code configured for causing a computer to perform steps of:

(a) receiving as input a test value of an electrical parameter measured for each of a plurality of identically designed electrical circuits;

(b) identifying one of the identically designed electrical circuits as an outlier for which the test value of the electrical parameter varies from a mean test value of the electrical parameter for the plurality of identically designed electrical circuits by at least a selected difference;

(c) monitoring the test value while subjecting a location on the outlier to a stimulus to detect a change in the test value as a function of the location; and

(d) generating as output the location for which the change in the test value is detected to identify a defect in the outlier;

such that each of steps (a), (b), (c) and (d) is performed by the computer.

12. The computer program product of claim 11 wherein step (c) comprises subjecting the outlier to a beam of at least one of optical radiation, thermal radiation, and charged particles.

13. The computer program product of claim 11 wherein step (a) comprises measuring an electrical parameter comprising at least one of minimum operating voltage, maximum operating voltage, minimum operating frequency, maximum operating frequency, static leakage current, and dynamic leakage current.

14. The computer program product of claim 13 comprising measuring the electrical parameter as a function of at least one of a test vector, a clock cycle, a supply voltage, and a device logic state.

15. The computer program product of claim 11 comprising calculating the selected difference as a multiple of a standard deviation of the electrical parameter for the plurality of identically designed electrical circuits.

16. The computer program product of claim 11 wherein step (c) comprises applying the stimulus to one of a plurality of scanned coordinates on the outlier.

17. The computer program product of claim 11 wherein step (c) comprises applying the stimulus to successively smaller areas on the outlier.

18. The computer program product of claim 11 wherein step (a) comprises measuring the electrical parameter for each of a plurality of identically designed electrical circuits having no stuck-at faults.

19. The computer program product of claim 11 wherein step (a) comprises measuring the electrical parameter for each of a plurality of identically designed electrical circuits having no transition delay faults.

20. The computer program product of claim 11 wherein step (a) comprises measuring a test value of an electrical parameter that does not include operating current.

21. An apparatus comprising:

a measuring apparatus for measuring a test value of an electrical parameter for each of a plurality of identically designed electrical circuits to identify an outlier;

an apparatus for subjecting the outlier to a stimulus; and

a monitoring device for monitoring the test value while subjecting a location on the outlier to the stimulus to detect a change in the test value as a function of the location.

Assignments (11)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059720/0223 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044887/0109 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 3, 2015
From: LSI CORPORATION
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035390/0388 →
CHANGE OF NAME Recorded Jun 6, 2014
From: LSI LOGIC CORPORATION
To: LSI CORPORATION
Reel/Frame 033102/0270 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
MERGER Recorded Feb 19, 2008
From: LSI SUBSIDIARY CORP.
To: LSI CORPORATION
Reel/Frame 020548/0977 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 29, 2005
From: HAEHN, STEVEN L.; BENWARE, ROBERT B.
To: LSI LOGIC CORPORATION
Reel/Frame 017425/0070 →