Process for forming an electronic device including a fin-type structure
View Patent ↗A process for forming an electronic device can include forming a semiconductor fin of a first height for a fin-type structure and removing a portion of the semiconductor fin such that the semiconductor fin is shortened to a second height. In accordance with specific embodiment a second semiconductor fin can be formed, each of the first and the second semiconductor fins having a different height representing a channel width. In accordance with another specific embodiment a second and a third semiconductor fin can be formed, each of the first, the second and the third semiconductor fins having a different height representing a channel width.
1. A process for forming an electronic device comprising:
forming a first semiconductor fin for a first fin-type transistor structure over a support layer of a substrate, wherein, the first semiconductor fin has a first height; and
removing a portion of the first semiconductor fin to provide the first semiconductor fin with a second height, wherein the second height is smaller than the first height.
2. The process of claim 1 , further comprising:
forming a second semiconductor fin for a second fin-type transistor structure over the support layer prior to removing the portion of the first semiconductor fin, wherein the second semiconductor fin has the first height.
3. The process of claim 2 wherein forming the first semiconductor fin and forming the second semiconductor fin comprises forming the first semiconductor fin and the second semiconductor fin from a semiconductor layer of the substrate.
4. The process of claim 2 , wherein forming the second semiconductor fin occurs at a substantially same time as forming the first semiconductor fin.
5. The process of claim 2 , wherein the first semiconductor fin comprises a p-channel device, and the second semiconductor fin comprises an n-channel device.
6. The process of claim 2 , further comprising:
doping the first semiconductor fin with a n-type dopant after removing the portion of the first semiconductor fin; and
doping the second semiconductor fin with an p-type dopant after removing the portion of the first semiconductor fin.
7. The process of claim 2 , wherein forming the first semiconductor fin comprises forming the first semiconductor fin from an n-doped semiconductor region, and forming the second semiconductor fin comprises forming the second semiconductor fin from a p-doped semiconductor region.
8. The process of claim 2 wherein the second semiconductor fin has the first height after removing the portion of the first semiconductor fin.
9. The process of claim 2 , wherein forming the first semiconductor fin includes forming the first semiconductor fin from a semiconductor material with a ( 110 ) crystal plane for the fin sidewall.
10. The process of claim 2 , wherein forming the second semiconductor fin includes forming the second semiconductor fin from a semiconductor material with a ( 110 ) crystal plane for the fin sidewall.
11. A process of claim 2 , further comprising:
forming a third semiconductor fin for a third fin-type transistor structure prior to removing the portion of the first semiconductor fin portion, the third semiconductor fin having the first height.
12. The process of claim 11 , further comprising:
removing a portion of the third fin-type transistor structure to provide the third semiconductor fin with a third height, wherein the third height is between the first height and the second height.
13. A process for forming an electronic device, comprising:
forming a first semiconductor fin over a support layer of a substrate;
forming a second semiconductor fin over the support layer;
removing a portion of the first semiconductor fin to provide a first fin-type transistor structure a first channel region having a first channel width; and
removing a portion of the second semiconductor fin to provide a second fin-type transistor structure a second channel region having a second channel width.
14. A process of claim 13 , wherein the first channel region is a channel region of an n-channel transistor.
15. A process of claim 13 , wherein the first channel width is larger than the second channel width.
16. A process of claim 13 , wherein the first channel region is a channel region of a p-channel transistor.
17. A process of claim 13 , further comprising:
forming a third semiconductor fin over the support layer of the substrate to provide a third fin-type transistor structure a third channel region having a third channel width different from the first and the second channel widths, wherein the third channel width is larger than the first and second channel widths.
18. A process for forming an electronic device, comprising:
forming a first semiconductor fin for a first fin-type transistor structure, the first semiconductor fin having a first height;
forming a second semiconductor fin for a second fin-type transistor structure, the second semiconductor fin having the first height;
removing a portion of the second semiconductor fin to provide the second semiconductor fin with a second height smaller than the first height; and
forming a first gate electrode overlying the first semiconductor fin wherein a first channel region of the first semiconductor fin has a first channel width approximately equal to twice the first height; and
forming a second gate electrode overlying the second semiconductor fin wherein a second channel region within the second semiconductor fin has a second channel width approximately equal to twice the second height.
19. The semiconductor device of claim 18 , further comprising:
forming a third semiconductor fin for a third fin-type structure, the third semiconductor fin having the first height;
removing a portion of the third semiconductor fin to provide the third semiconductor fin, a third height smaller than the second height; and
forming a third gate electrode overlying the third semiconductor fin, wherein the first semiconductor fin and the third semiconductor fin have different crystal orientation planes for the fin sidewalls.
20. The semiconductor device of claim 19 , wherein the first channel region and a third channel region have opposing conductivity types.