ESD protection circuit for low voltages
View Patent ↗An ESD protection circuit is provided having a first field-effect transistor, which has a first drain terminal, a first source terminal and a first control terminal, and having an input network which, in the event that a first voltage present between the first drain terminal and the first source terminal crosses a threshold value, alters a second voltage that appears between the first control terminal and the first source terminal. The input network contains a second field-effect transistor, complementary to the first field-effect transistor, having a second drain terminal, a second source terminal and a second control terminal, wherein the first drain terminal is connected to the second source terminal and, through a first resistance, to the second control terminal, and the second drain terminal is connected to the first control terminal and, through a second resistance, to the first source terminal.
1. A circuit comprising:
a first field-effect transistor having a first drain terminal, a first source terminal, and a first control terminal;
a second field-effect transistor having a second drain terminal, a second source terminal, and a second control terminal, the second field-effect transistor being complementary to the first field-effect transistor, the first drain terminal being coupled directly to the second source terminal and, through a first resistance, to the second control terminal, the second drain terminal being coupled to the first control terminal and, through a second resistance, to the first source terminal; and
a Zener diode having a cathode coupled to the second control terminal;
a gate-source capacitance of the second field-effect transistor corresponding to a depletion-layer capacitance of the Zener diode.
2. The circuit of claim 1 , further comprising a third resistance coupling the Zener diode to the first source terminal.
3. The circuit of claim 1 , wherein:
the first transistor is an n-channel field-effect transistor; and
the second transistor is a p-channel field-effect transistor.
4. The circuit of claim 1 , wherein the second field-effect transistor has a smaller channel area than the first field-effect transistor.
5. A circuit comprising:
an n-channel field-effect transistor having a first drain terminal, a first source terminal, and a first control terminal;
a p-channel field-effect transistor having a second drain terminal, a second source terminal, and a second control terminal, the first drain terminal being coupled directly to the second source terminal and, through a first resistance, to the second control terminal, the second drain terminal being coupled to the first control terminal and, through a second resistance, to the first source terminal; and
a Zener diode coupled to the second control terminal;
a gate-source capacitance of the p-channel field-effect transistor corresponding to a depletion-layer capacitance of the Zener diode.
6. The circuit of claim 5 , wherein a cathode of the Zener diode is coupled to the second control terminal.
7. The circuit of claim 5 , further comprising a third resistance coupling the Zener diode to the first source terminal.
8. The circuit of claim 5 , wherein the p-channel field-effect transistor has a smaller channel area than the n-channel field-effect transistor.
9. A circuit comprising:
an n-channel field-effect transistor having a first drain terminal, a first source terminal, and a first control terminal;
a p-channel field-effect transistor having a second drain terminal, a second source terminal, and a second control terminal, the first drain terminal coupled directly to the second source terminal and, through a first resistance, to the second control terminal, the second drain terminal coupled to the first control terminal and, through a second resistance, to the first source terminal; and
a Zener diode coupled to the second control terminal and, through a third resistance, to the first source terminal;
a gate-source capacitance of the p-channel field-effect transistor corresponding to a depletion-layer capacitance of the Zener diode.
10. The circuit of claim 9 , wherein a cathode of the Zener diode is coupled to the second control terminal.
11. The circuit of claim 9 , wherein the p-channel field-effect transistor has a smaller channel area than the n-channel field-effect transistor.