Wideband ultra low noise amplifier
View Patent ↗A circuit and method of reducing noise in the circuit comprises a first transistor and an amplifier operatively connected to the first transistor, wherein the amplifier comprises a plurality of transistors and is adapted to amplify an input signal, and wherein the input signal is differentially captured at an output of the first transistor and the amplifier. Preferably, the plurality of transistors comprises a second transistor and a third transistor. Furthermore, a noise level of the first transistor and the third transistor are preferably cancelled. The size of the second transistor may be approximately 1/50Ω. Preferably, a gain on an amplifier stage formed by the second transistor and the third transistor is adapted to be increased. Moreover, an equivalent transconductance of the amplifier is preferably independent of an impedance matching on the amplifier. Preferably, a noise figure level of the circuit is less than approximately 1 dB.
1. A circuit comprising:
a first transistor; and
an amplifier operatively connected to said first transistor, wherein said amplifier comprises a plurality of transistors including a second transistor and a third transistor and is adapted to amplify an input signal, wherein a node between the second and third transistors is directly connected to a gate of said first transistor;
wherein said input signal is differentially captured at an output of said first transistor and said amplifier.
2. The circuit of claim 1 , all the limitations of which are incorporated herein by reference, wherein an input resistance of said amplifier is approximately 50Ω and equals 1/[g m1 (1+(g m2 /g m3 ))], wherein a noise figure level of said circuit equals 1+[γ/(1+(g m2 /g m3 ))], and wherein g m1 is a transconductance of said primary transistor, g m2 is a transconductance of said second transistor, g m3 is a transconductance of said third transistor, and γ is a bias-dependent parameter.
3. The circuit of claim 1 , all the limitations of which are incorporated herein by reference, wherein a noise level of said first transistor and said third transistor are cancelled.
4. The circuit of claim 2 , all the limitations of which are incorporated herein by reference, wherein a size of said second transistor is approximately 1/50Ω, and wherein the g m2 /g m3 ratio can be adjusted to increase a gain on said amplifier and reduce said noise figure level of said circuit.
5. The circuit of claim 1 , all the limitations of which are incorporated herein by reference, wherein a gain on an amplifier stage formed by said second transistor and said third transistor is adapted to be increased.
6. The circuit of claim 1 , all the limitations of which are incorporated herein by reference, wherein an equivalent transconductance of said amplifier is independent of an impedance matching on said amplifier.
7. The circuit of claim 1 , all the limitations of which are incorporated herein by reference, wherein a noise figure level of said circuit is less than approximately 1 dB, wherein an overall output current is sensed differentially and equals an output current to said first transistor minus an output current to said third transistor, and wherein said overall output current is fed back to a resistive load of said circuit.
8. A wideband low noise amplifying circuit comprising:
a primary transistor; and
a pair of secondary transistors adapted to amplify an input signal and operatively connected to said primary transistor, wherein said pair of secondary transistors comprises a second transistor and a third transistor, wherein a node between the second and third transistors is directly connected to a gate of said primary transistor, and wherein said input signal is differentially captured at an output of said primary transistor and said third transistor.
9. The circuit of claim 8 , all the limitations of which are incorporated herein by reference, wherein a noise level of said primary transistor and said third transistor are cancelled.
10. The circuit of claim 8 , all the limitations of which are incorporated herein by reference, wherein a size of said second transistor is approximately 1/50Ω.
11. The circuit of claim 8 , all the limitations of which are incorporated herein by reference, wherein a gain on an amplifier stage formed by said second transistor and said third transistor is adapted to be increased.
12. The circuit of claim 8 , all the limitations of which are incorporated herein by reference, wherein an equivalent transconductance of the second and third transistors is independent of an impedance matching on said second and third transistors.
13. The circuit of claim 8 , all the limitations of which are incorporated herein by reference, wherein a noise figure level of said circuit is less than approximately 2 dB.
14. A method of reducing noise of an amplified signal in a circuit, said method comprising:
operatively connecting a first transistor to an amplifier, wherein said amplifier comprises a plurality of transistors comprising a second transistor and a third transistor, wherein a node between the second and third transistors is directly connected to a gate of said first transistor;
inputting a signal to said first transistor and said amplifier;
differentially capturing the inputted signal at an output of said first transistor and said amplifier; and
amplifying the differentially captured input signal.
15. The method of claim 14 , all the limitations of which are incorporated herein by reference, wherein an input resistance of said amplifier is approximately 50Ω and equals 1/[g m1 (1+(g m2 /g m3 ))], wherein a noise figure level of said circuit equals 1+[γ/(1+(g m2 /g m3 ))], and wherein g m1 is a transconductance of said primary transistor, g m2 is a transconductance of said second transistor, g m3 is a transconductance of said third transistor, and γ is a bias-dependent parameter.
16. The method of claim 14 , all the limitations of which are incorporated herein by reference, further comprising canceling a noise level of said first transistor and said third transistor.
17. The method of claim 15 , all the limitations of which are incorporated herein by reference, further comprising configuring a size of said second transistor to approximately 1/50Ω, and adjusting the g m2 /g m3 ratio to increase a gain of said amplifier and reduce said noise figure level of said circuit.
18. The method of claim 14 , all the limitations of which are incorporated herein by reference, further comprising increasing a gain on an amplifier stage formed by said second transistor and said third transistor.
19. The method of claim 14 , all the limitations of which are incorporated herein by reference, wherein an equivalent transconductance of said amplifier is independent of an impedance matching on said amplifier.
20. The method of claim 14 , all the limitations of which are incorporated herein by reference, wherein a noise figure level of said circuit is less than approximately 1 dB, wherein an overall output current is sensed differentially and equals an output current to said first transistor minus an output current to said third transistor, and wherein said overall output current is fed back to a resistive load of said circuit.