High-speed logic signal level shifter
View Patent ↗A high speed logic signal level shifter is comprised of: a logic signal buffer for receiving logic signal information and having true and complement state differential outputs; a binary flip-flop circuit with set and reset inputs; a first coupling capacitor connected from the true buffer output to the set input of the binary flip-flop circuit; and a second coupling capacitor connected from the complement buffer output to the reset input of the binary flip-flop circuit. The high speed logic signal level shifter transfers a fast logic signal across a high voltage difference by making use of rapid voltage changes transmitted through small capacitors. The signal changes carried by the capacitors are about 10 times faster than any expected voltage transient on VPP or VNN. Furthermore, the differential coupling circuit is used to provide enhanced protection against undesired circuit switching during supply voltage changes.
1. A high speed logic signal level shifter comprising:
a logic signal buffer having first and second outputs, wherein the logic signal buffer receives an input signal and generates a first set of current pulses, the logic signal buffer generates a second set of current pulses when the input signal transitions from a first state to a second state;
a binary flip-flop circuit coupled to the logic signal buffer comprising a first inverter and a first NAND gate connected in a feedback loop so an output of the first inverter connects directly to an input of the first NAND gate, and an output of the first NAND gate connects directly to an input of the first inverter;
a first coupling capacitor directly attached to the first output of the logic signal buffer and to the output of the second inverter of the binary flip-flop circuit, the first coupling capacitor forcing a change of state of the binary flip flop based on one of the first set of current pulses and the second set of current pulses generated by the logic signal buffer; and
a second coupling capacitor directly attached to the second output of the logic signal buffer and to the output of the first inverter of the binary flip-flop circuit, the second coupling capacitor forcing a change of state of the binary flip flop based on one of the first set of current pulses and the second set of current pulses generated by the logic signal buffer;
a reset signal circuit for setting the binary flip-flop to a known state with a reset signal; and
a DC coupled level translator for connecting the reset signal circuit to the binary flip-flop circuit;
wherein the logic signal buffer has a peak-to-peak output voltage approximately equal to an input signal swing of the binary flip-flop.
2. The high speed logic signal level shifter of claim 1 , further comprising an output buffer coupled to the binary flip flop circuit.
3. The high speed logic signal level shifter of claim 1 , further comprising a second NAND gate for preventing an input to the logic signal buffer during times that the reset signal is active.
4. The high speed logic signal level shifter of claim 3 , further comprising a delay circuit coupled in series with at least one reset signal path to the second NAND gate.
5. The high speed logic signal level shifter of claim 1 , further comprising a power supply under voltage detection circuit to provide the reset signal.
6. The high speed logic signal level shifter of claim 1 , further comprising a means for detecting a rate of change of at least one power supply voltage, and providing the reset signal whenever the at least on power supply voltage rate of change exceeds a chosen value.
7. The high speed logic signal level shifter of claim 1 , further comprising a logic comparison circuit having a first input coupled to the logic signal buffer, and a second input coupled to the binary flip-flop.
8. The high speed logic signal level shifter of claim 7 , wherein the logic comparison circuit output is coupled to at least one of the set or reset inputs of the binary flip-flop.
9. The high speed logic signal level shifter of claim 7 , wherein the logic comparison circuit includes a time delay.
10. A bipolar high voltage driver circuit comprising:
a high voltage P-channel MOSFET transistor with its source terminal connected to a high voltage positive supply;
a high voltage N-channel MOSFET transistor with its source terminal connected to a high voltage negative supply;
a first high speed logic signal level shifter comprising:
a logic signal buffer having an input and a differential output providing true and complimentary outputs;
a binary flip-flop circuit with set and reset inputs coupled to the logic signal buffer;
a first coupling capacitor coupled to the true output of the logic signal buffer and to the set input of the binary flip-flop circuit; and
a second coupling capacitor coupled to the complementary output of the logic signal buffer and to the reset input of the binary flip-flop circuit;
wherein the output buffer of the first high speed logic signal level shifter biased to drive the gate of the high voltage P-channel MOSFET transistor; and
a second high speed logic signal level shifter according to claim 2 , with the output buffer of the second high speed logic signal level shifter biased to drive the gate of the high voltage N-channel MOSFET transistor.