Semiconductor assembly including chip scale package and second substrate with exposed surfaces on upper and lower sides

1. A semiconductor assembly comprising:

a first package comprising a first package substrate having a die attach side and a land side, the first package including at least one die affixed to, and electrically interconnected by wires bonds with, the die attach side of the first package substrate and encapsulated in a first encapsulant; and

a second substrate, wherein the first package is inverted in relation to the substrate, and wherein z-interconnection of the first package substrate and the second substrate is by wire bonds connecting the first package substrate and the second substrate, the assembly further being encapsulated in a second encapsulant so that both the second substrate at one side of the assembly and a portion of the first package substrate at an opposite side of the assembly are exposed, whereby second level interconnection and interconnection with additional components may be made.

2. The semiconductor assembly of claim 1 further comprising second level interconnections at the exposed land side of the second substrate.

3. The semiconductor assembly of claim 1 further comprising second level interconnections at the exposed portion of the land side of the first package substrate.

4. The semiconductor assembly of claim 1 wherein the second substrate is a land grid array package.

5. The semiconductor assembly of claim 1 wherein the first package is a matrix molded and saw singulated chip scale package.

6. The semiconductor assembly of claim 1 , further comprising an assembly encapsulation.

7. The semiconductor assembly of claim 1 wherein the first package is a stacked die chip scale package.

8. The semiconductor assembly of claim 1 wherein the die in the first package is interconnected with the first package substrate by wire bonding.

9. The semiconductor assembly of claim 1 wherein the die in the first package is interconnected with the first package substrate by flip chip interconnection.

10. A semiconductor assembly comprising a first encapsulant encapsulating a land grid array substrate exposed at one side of the assembly and encapsulating a portion of a chip scale package substrate having a further encapsulated wire bonded die exposed at the opposite side of the assembly, further comprising second level interconnection at the exposed portion of the chip scale package substrate and having at least one additional component mounted at the exposed land grid array substrate.

11. The package assembly of claim 10 wherein the additional component includes at least one of: a ball grid array package, an additional land grid array package, a quad flat package, a quad flat nonleaded package, a lead frame chip scale package, a wire bonded die, a flip chip die, an optical sensor package, a micro-electro-mechanical sensor package, or a passive device.

12. A semiconductor assembly comprising a first encapsulant encapsulating a land grid array substrate exposed at one side of the assembly and encapsulating a portion of a chip scale package substrate having a further encapsulated wire bonded die exposed at the opposite side of the assembly, further comprising second level interconnection at the exposed land grid array substrate and having at least one additional component mounted at the exposed portion of the chip scale package substrate.

13. The package assembly of claim 12 wherein the additional component includes at least one of: a ball grid array package, an additional land grid array package, a quad flat package, a quad flat nonleaded package, a lead frame chip scale package, a wire bonded die, a flip chip die, an optical sensor package, a micro-electro-mechanical sensor package, or a passive device.

14. A method for making a semiconductor assembly, comprising: providing an LGA substrate; providing a singulated CSP; applying an adhesive onto the surface of the molding of the CSP package; inverting the CSP and placing the inverted CSP onto LGA substrate; curing the adhesive; performing a plasma clean on a land side of the CSP; wire bonding to form z-interconnection between the LGA substrate and the land side of the CSP; performing a plasma clean; performing a molding operation to enclose a side of the LGA, the z-interconnection wire bonds and wire loops, the edges of the CSP, and the marginal area on the land side of the CSP, leaving exposed the land side of the LGA substrate and an area of the land side of the CSP substrate located within a marginal area; and attaching second level interconnect solder balls to sites on the exposed area of the CSP substrate.

15. The method of claim 14 , further comprising affixing and electrically connecting an additional component at the exposed side of the LGA subsstrate.

16. A method for making a semiconductor assembly, comprising: providing an LGA substrate; providing a singulated CSP; applying an adhesive onto the surface of the molding of the CSP package; inverting the CSP and placing the inverted CSP onto LGA substrate; curing the adhesive; performing a plasma clean on a land side of the CSP; wire bonding to form z-interconnection between the LGA substrate and the land side of the CSP; performing a plasma clean; performing a molding operation to enclose a side of the LGA, the z-interconnection wire bonds and wire loops, the edges of the CSP, and the marginal area on the land side of the CSP, leaving exposed the land side of the LGA substrate and an area of the land side of the CSP substrate located within a marginal area; and attaching second level interconnect solder balls to sites on the exposed side of the LGA package substrate.

17. The method of claim 16 , further comprising affixing and electrically connecting an additional component at the exposed portion of the CSP substrate.