Radio frequency power detector
View Patent ↗RF power detector employing an envelope amplifier circuit and a current mirror circuit. The output of the current mirror circuit supplies a bias voltage for biasing the output of the envelope amplifier circuit. Furthermore, the output of the envelope amplifier circuit is fed back to the output of the current mirror circuit so as to reduce the magnitude of the bias signal according to the magnitude of the amplified RF signal envelope. In this manner, the overall gain of the RF power detector can be selectively reduced, resulting in an RF power detector having a more linearized dynamic range and greater ability to compensate for variation in gain caused by temperature.
1. A radio frequency power detector, comprising:
an input configured to receive a first radio frequency signal;
an envelope amplifier circuit in electrical communication with the input, and configured to output a second radio frequency signal corresponding to an amplified envelope of the first radio frequency signal; and
a current mirror circuit in electrical communication with the envelope amplifier circuit, and configured to output a bias signal for biasing the second radio frequency signal;
wherein the envelope amplifier circuit is further configured to feed the second radio frequency signal back to the current mirror circuit so as to reduce a magnitude of the bias signal according to a magnitude of the second radio frequency signal.
2. The radio frequency power detector of claim 1 wherein the biased second radio frequency signal has an associated output power that can vary over a range, and wherein the envelope amplifier circuit is further configured to feed the second radio frequency signal back to the current mirror circuit so as to facilitate the linearization of the biased second radio frequency signal over the range of the output power.
3. The radio frequency power detector of claim 2 wherein the linearized range of the output power is at least approximately 25 dB.
4. The radio frequency power detector of claim 1 wherein the magnitude of the bias signal is reduced so as to reduce a quiescent output voltage output from the current mirror circuit.
5. The radio frequency power detector of claim 1 wherein the input further comprises a tapping network configured to directionally couple the input to the envelope amplifier circuit.
6. The radio frequency power detector of claim 5 wherein the tapping network further comprises a capacitor and a resistor, the capacitor having a first terminal in electrical communication with the input and a second terminal in electrical communication with a first terminal of the resistor, the resistor having a second terminal in electrical communication with the envelope amplifier circuit.
7. The radio frequency power detector of claim 5 wherein the tapping network is further configured for electrical connection to an interstage of a power amplifier.
8. The radio frequency power detector of claim 1 :
wherein the envelope amplifier circuit further comprises a first voltage source and a first transistor; and
wherein the first transistor has a collector terminal in electrical communication with the first voltage source, a base terminal in electrical communication with the input, and an emitter terminal configured to emit the second radio frequency signal.
9. The radio frequency power detector of claim 8 :
wherein the current mirror circuit further comprises a second voltage source and a second transistor; and
wherein the second transistor has a collector terminal in electrical communication with the second voltage source, a base terminal in electrical communication with the input, and an emitter terminal in electrical communication with the emitter terminal of the first transistor, the emitter terminal of the second transistor configured to emit the bias signal and to receive the second radio frequency signal.
10. The radio frequency power detector of claim 9 wherein the second voltage source is further configured to provide a reference voltage to at least one of a linear power amplifier and a saturated power amplifier.
11. The radio frequency power detector of claim 8 further comprising a first low pass filter having a first filter resistor in electrical parallel with a first filter capacitor, wherein the first filter resistor and the first filter capacitor each have a first terminal in electrical communication with the emitter terminal of the first transistor and the emitter terminal of the second transistor, and a grounded second terminal.
12. The radio frequency power detector of claim 9 further comprising a second low pass filter having a second filter resistor in electrical series with a second filter capacitor;
wherein the second filter resistor has a first terminal in electrical communication with the emitter terminal of the first transistor and the emitter terminal of the second transistor, and a second terminal in electrical communication with a first terminal of the second filter capacitor; and
wherein the second filter capacitor has a grounded second terminal.
13. A method of detecting the power of radio frequency signals, comprising:
providing an input configured to receive a first radio frequency signal;
providing an envelope amplifier circuit in electrical communication with the input, and configured to output a second radio frequency signal corresponding to an amplified envelope of the first radio frequency signal; and
providing a current mirror circuit in electrical communication with the envelope amplifier circuit, and configured to output a bias signal for biasing the second radio frequency signal;
wherein the envelope amplifier circuit is further configured to feed the second radio frequency signal back to the current mirror circuit so as to reduce a magnitude of the bias signal according to a magnitude of the second radio frequency signal.
14. The method of claim 13 wherein the biased second radio frequency signal has an associated output power that can vary over a range, and wherein the envelope amplifier circuit is further configured to feed the second radio frequency signal back to the current mirror circuit so as to facilitate the linearization of the biased second radio frequency signal over the range of the output power.
15. The method of claim 14 wherein the linearized range of the output power is at least approximately 25 dB.
16. The method of claim 13 wherein the magnitude of the bias signal is reduced so as to reduce a quiescent output voltage output from the current mirror circuit.
17. The method of claim 13 wherein the input further comprises a tapping network configured to directionally couple the input to the envelope amplifier circuit.
18. The method of claim 17 wherein the tapping network further comprises a capacitor and a resistor, the capacitor having a first terminal in electrical communication with the input and a second terminal in electrical communication with a first terminal of the resistor, the resistor having a second terminal in electrical communication with the envelope amplifier circuit.
19. The method of claim 17 wherein the tapping network is further configured for electrical connection to an interstage of a power amplifier.
20. The method of claim 13 :
wherein the envelope amplifier circuit further comprises a first voltage source and a first transistor; and
wherein the first transistor has a collector terminal in electrical communication with the first voltage source, a base terminal in electrical communication with the input, and an emitter terminal configured to emit the second radio frequency signal.
21. The method of claim 20 :
wherein the current mirror circuit further comprises a second voltage source and a second transistor; and
wherein the second transistor has a collector terminal in electrical communication with the second voltage source, a base terminal in electrical communication with the input, and an emitter terminal in electrical communication with the emitter terminal of the first transistor, the emitter terminal of the second transistor configured to emit the bias signal and to receive the second radio frequency signal.
22. The method of claim 21 wherein the second voltage source is further configured to provide a reference voltage to at least one of a linear power amplifier and a saturated power amplifier.
23. The method of claim 20 further comprising a first low pass filter having a first filter resistor in electrical parallel with a first filter capacitor, wherein the first filter resistor and the first filter capacitor each have a first terminal in electrical communication with the emitter terminal of the first transistor and the emitter terminal of the second transistor, and a grounded second terminal.
24. The method of claim 21 further comprising a second low pass filter having a second filter resistor in electrical series with a second filter capacitor;
wherein the second filter resistor has a first terminal in electrical communication with the emitter terminal of the first transistor and the emitter terminal of the second transistor, and a second terminal in electrical communication with a first terminal of the second filter capacitor; and
wherein the second filter capacitor has a grounded second terminal.