Selective contact formation using masking and resist patterning techniques
View Patent ↗A method for manufacturing a semiconductor device including selective conductive contacts includes the step of depositing a resist over first and second memory device components, each of the first and second components comprising junctions formed in the substrate and a gate formed on the substrate between the junctions. The resist is then removed from the second components to thereby form a resist opening above each of the second component control gates and junctions. The resist is then etched to thereby expose each of the first component control gates but not the substrate surrounding the first component control gates. Conductive contacts are then formed on the exposed first component control gates, and the second component control gates and junctions.
1. A method for manufacturing a semiconductor device including selective conductive contacts, the method comprising:
depositing a resist over first and second memory device components, each of the first components comprising a gate formed on a substrate, and each of the second components comprising junctions formed in the substrate and a gate formed on the substrate between the junctions;
removing the resist from the second components, and thereby forming a resist opening above each of the second component control gates and junctions;
etching the resist after the step of removing and exposing each of the first component control gates but not the substrate surrounding the first component control gates; and
forming conductive contacts on the exposed first component control gates, and the second component control gates and junctions.
2. The method according to claim 1 , wherein the memory device comprises a core region having wordlines and bitlines formed from at least some of the first components, and a peripheral region having logic elements formed from at least some of the second components, the step of depositing a resist over first and second memory device components includes depositing the resist over both the core region and the peripheral region, and the step of removing the resist from the second components includes removing the resist from the entire peripheral region.
3. The method according to claim 2 , wherein the core region includes doped junctions embedded in the substrate, and wherein the step of depositing a resist over first and second memory device components includes depositing the resist over the doped junctions.
4. The method according to claim 1 , wherein the step of etching the resist comprises a dry etching process.
5. The method according to claim 1 , wherein the step of forming conductive contacts comprises:
depositing metal onto the exposed first component control gates, and also onto the second component control gates and junctions; and
reacting the metal with a silicon-containing material included in the first component control gates and the second component control gates and junctions, to form conductive metal silicide contacts.
6. The method according to claim 5 , wherein the step of depositing metal comprises depositing a metal selected from the group consisting of cobalt, nickel, titanium, tantalum, platinum, palladium, rhodium, and mixtures thereof.
7. The method according to claim 1 , wherein the step of removing the resist from the second components exposes any oxide formed on each of the second component control gates and junctions, and the step of etching the resist exposes any oxide formed on the first component control gates, the method further comprising:
etching any oxide formed on each of the second component control gates and junctions, and any oxide formed on the first component control gates before the step of forming the conductive contacts.
8. The method according to claim 1 , further comprising the step of:
forming an oxide at least on the substrate surrounding the first component control gates prior to forming the conductive contacts.
9. The method according to claim 8 , further comprising the step of:
stripping the resist from the substrate surrounding the first component control gates to expose the oxide formed thereon prior to the step of forming the conductive contacts.
10. The method according to claim 1 , further comprising the step of:
stripping the resist from the substrate surrounding the first component control gates after the step of forming the conductive contacts.
11. A method for manufacturing a semiconductor device including selective conductive contacts, the method comprising:
depositing a first layer of resist over first and second memory device components, each of the first components comprising a control gate formed on a substrate, and each of the second components comprising junctions formed in the substrate and a control gate formed on the substrate between the junctions;
polishing the first layer of resist and thereby exposing at least the first component control gates but not the substrate surrounding the first component control gates;
depositing a second layer of resist onto the first layer of resist and over the first components, leaving an exposed region of the first resist surrounding the second components;
simultaneously removing the entire second layer of resist, and the exposed region of the first layer of resist, and thereby exposing each of the second component control gates and junctions; and
forming conductive contacts on the exposed first component control gates, and the second component control gates and junctions.
12. The method according to claim 11 , wherein the memory device comprises a core region having wordlines and bitlines formed from at least some of the first components, and a peripheral region having logic elements formed from at least some of the second components, the step of depositing a first layer of resist over first and second memory device components includes depositing the resist over both the core region and the peripheral region, and the step of removing the exposed region of the first layer of resist includes removing the first layer of resist from the entire peripheral region.
13. The method according to claim 12 , wherein the core region includes doped junctions embedded in the substrate, and wherein the step of depositing a first layer of resist over first and second memory device components includes depositing the resist over the doped junctions.
14. The method according to claim 11 , wherein the step of polishing the resist comprises a chemical-mechanical polishing process.
15. The method according to claim 11 , wherein the step of forming conductive contacts comprises:
depositing metal onto the exposed first component control gates, and also onto the second component control gates and junctions; and
reacting the metal with a silicon-containing material included in the first component control gates and the second component control gates and junctions, to form conductive metal silicide contacts.
16. The method according to claim 15 , wherein the step of depositing metal comprises depositing a metal selected from the group consisting of cobalt, nickel, titanium, tantalum, platinum, palladium, rhodium, and mixtures thereof.
17. The method according to claim 11 , wherein the step of simultaneously removing the entire second layer of resist, and the exposed region of the first layer of resist, exposes any oxide formed on each of the second component control gates and junctions, and any oxide formed on the first component control gates, the method further comprising:
etching any oxide formed on each of the second component control gates and junctions, and any oxide formed on the first component control gates before the step of forming the conductive contacts.
18. The method according to claim 11 , further comprising the step of:
forming an oxide at least on the substrate surrounding the first component control gates prior to forming the conductive contacts.
19. The method according to claim 18 , further comprising the step of:
stripping the first layer of resist from the substrate surrounding the first component control gates to expose the oxide formed thereon prior to the step of forming the conductive contacts.
20. The method according to claim 11 , further comprising the step of:
stripping the first layer of resist from the substrate surrounding the first component control gates after the step of forming the conductive contacts.