Vertical replacement-gate silicon-on-insulator transistor
View Patent ↗An architecture for creating a vertical silicon-on-insulator MOSFET. Generally, an integrated circuit structure includes a semiconductor area with a major surface formed along a plane and a first source/drain contact region formed in the surface. A relatively thin single crystalline layer is oriented vertically above the major surface and comprises a first source/drain doped region over which is located a doped channel region, over which is located a second source/drain region. An insulating layer is disposed adjacent said first and said second source/drain regions and said channel region, serving as the insulating material of the SOI device. In another embodiment, insulating material is adjacent only said first and said second source/drain regions. A conductive region is adjacent the channel region for connecting the back side of the channel region to ground, for example, to prevent the channel region from floating. In an associated method of manufacturing the semiconductor device, a first source/drain region is formed in a relatively thin vertical layer of single crystalline material. A MOSFET gate region, including a channel and a gate electrode, is formed over the first source/drain region. A second source/drain region is then formed over the channel, the regions being appropriately doped to effect MOSFET action.
1. A process for fabricating a vertical silicon-on-insulator MOSFET comprising:
forming a first contact region selected from the group consisting of a source contact region and a drain contact region of a semiconductor device in a semiconductor substrate;
forming a multilayer stack comprising at least three layers of material over the first contact region, wherein the second layer is interposed between the first and the third layers, and wherein the first layer is proximate the first contact region;
forming a window in the at least three layers of material, wherein the window does not extend into the first contact region;
forming a semiconductor material along at least one vertical wall region of the window, wherein the semiconductor material comprises a first, a second and a third doped region, and wherein the first doped region is adjacent the first layer and is doped a first conductivity type and further is in electrical contact with the first contact region, and wherein the second doped region is adjacent the second layer and is doped a second conductivity type, and wherein the third doped region is adjacent the third layer and is doped the first conductivity type;
forming a first insulating surface adjacent the first doped region and extending toward the center of the window;
forming a second insulating surface adjacent the third doped region and extending toward the center of the window;
forming a conductive plug in the remaining open volume of the window, wherein a portion of the plug is in electrical contact with the second doped region on the surface of the second doped region facing the center of the window;
removing the second layer, thereby exposing at least a portion of the second doped region;
forming a gate dielectric layer in contact with the second doped region; and
forming a gate in contact with the gate dielectric layer.
2. The process of claim 1 wherein the second layer is removed by etching in an etchant, characterized by a first layer etch rate, a second layer etch rate, and a third layer etch rate, wherein the second layer etch rate is at least ten times faster than one of the first layer etch rate and the third layer etch rate.
3. The process of claim 1 wherein the material of the first, second and the third layer comprises doped insulating material, and wherein the process further comprises doping at least one of the first and the third doped regions by diffusing dopant from the first layer into the third doped region and by diffusing dopant from the third layer into the third doped region.
4. The process of claim 1 wherein the semiconductor material is doped in situ and wherein the material of at least one of the first layer and the third layer comprises doped insulating material, and wherein the process further comprises counterdoping the first doped region with dopant from the first layer and counterdoping the third doped region with dopant from the third layer.
5. The process of claim 4 wherein the step of forming the semiconductor material further comprises:
forming polycrystalline silicon along substantially the entire vertical distance of at least one vertical region of the interior surface of the window; and
melting the polycrystalline silicon to form single-crystalline silicon, and wherein the material of the first and the third layers is doped insulating material, and wherein during the step of melting, the dopants in the first layer are driven into the adjacent region of the semiconductor material to form the first doped region and dopants in the third layer are driven into the adjacent region of the semiconductor material to form the third doped region.