IP Library Granted Patent US 7,417,483
Granted Patent B2
US 7,417,483 · App. 11/423,764 · Granted Aug 26, 2008

Wide-band wide-swing CMOS gain enhancement technique and method therefor

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Quick Facts
Patent No.
US 7,417,483
App. No.
11/423,764
Granted
Aug 26, 2008
Kind
B2
Abstract

A regulated cascode current source has a current source circuit. A level shifter circuit is coupled to the current source circuit. The level shifter circuit has a circuit for independently controlling a voltage on a cascode node.

Claims (34)

1. A circuit apparatus comprising:

a current source circuit; and

a level shifter circuit coupled to the current source circuit wherein the level shifter circuit has a circuit for independently controlling a voltage on a cascode node;

wherein the current source comprises:

a first transistor having a first, second and third terminal, a second terminal of the first transistor coupled to the level shifter current, and a third terminal coupled to the cascode node; and

a second transistor having a first, second and third terminal, a first terminal of the second transistor coupled to the cascode node, a second terminal of the second transistor coupled to a voltage source, and a third terminal of the second transistor coupled to ground;

wherein the level shifter circuit comprises:

a third transistor having a first, second and third terminal, the first terminal of the third transistor coupled to a voltage supply, and the third terminal of the third transistor coupled to the current source circuit;

a fourth transistor having a first, second and third terminal, the first terminal of the fourth transistor coupled to the voltage supply, the second terminal of the fourth transistor coupled to the second terminal of the third transistor, and the third terminal of the fourth transistor coupled to a circuit for independently controlling a voltage on a cascode node;

a fifth transistor having a first, second and third terminal, the first terminal of the fifth transistor coupled to the third terminal of the third transistor, the second terminal of the fifth transistor coupled to the circuit for independently controlling the voltage on a cascode node, and the third terminal of the fifth transistor coupled to ground; and

the circuit for independently controlling the voltage on a cascode node coupled to the third terminal of the fourth transistor and to the cascode node, the circuit for independently controlling the voltage on a cascode node comprising:

a resistive element for independently controlling the voltage on a cascode node; and

a capacitive element coupled in parallel to the resistive element, the resistive element and the capacitive element coupled to the second terminal of the fifth transistor and the cascode node.

2. A circuit apparatus in accordance with claim 1 wherein the first transistor and the second transistor are NMOS transistors.

3. A circuit apparatus in accordance with claim 1 wherein the third and fourth transistors are PMOS transistors.

4. A circuit apparatus in accordance with claim 1 wherein the fifth transistor is an NMOS transistor.

5. A regulated cascode current source comprising:

an op amp;

a plurality of cascaded gain stages coupled to the op amp, wherein each cascaded gain stage comprises:

a current source circuit; and

a level shifter circuit coupled to the current source circuit wherein the level shifter circuit has a circuit for independently controlling a voltage on a cascode node;

wherein the current source comprises:

a first transistor having a first, second and third terminal, a second terminal of the first transistor coupled to the level shifter current, and a third terminal coupled to the cascode node; and

a second transistor having a first, second and third terminal, a first terminal of the second transistor coupled to the cascode node, a second terminal of the second transistor coupled to a voltage source, and a third terminal of the second transistor coupled to ground

wherein the level shifter circuit comprises:

a third transistor having a first, second and third terminals the first terminal of the third transistor coupled to a voltage supply, and the third terminal of the third transistor coupled to the current source circuit;

a fourth transistor having a first, second and third terminal, the first terminal of the fourth transistor coupled to the voltage supply, the second terminal of the fourth transistor coupled to the second terminal of the third transistor, and the third terminal of the fourth transistor coupled to a circuit for independently controlling a voltage on a cascode node;

a fifth transistor having a first, second and third terminal, the first terminal of the fifth transistor coupled to the third terminal of the third transistor, the second terminal of the fifth transistor coupled to the circuit for independently controlling the voltage on a cascode node, and the third terminal of the fifth transistor coupled to ground;

the circuit for independently controlling the voltage on a cascode node, the circuit for independently controlling the voltage on a cascode node comprises:

a resistive element for independently controlling the voltage on a cascode node; and

a capacitive element coupled in parallel to the resistive element, the resistive element and the capacitive element coupled to the second terminal of the fifth transistor and the cascode node.

6. A circuit apparatus in accordance with claim 5 wherein the first transistor and the second transistor are NMOS transistors.

7. A circuit apparatus in accordance with claim 5 wherein the third and fourth transistors are PMOS transistors.

8. A circuit apparatus in accordance with claim 5 wherein the fifth transistor is an NMOS transistor.

Assignments (16)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 059666/0545 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: MICROCHIP TECHNOLOGY INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041675/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2014
From: SUPERTEX LLC
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 034689/0257 →
CHANGE OF NAME Recorded Dec 19, 2014
From: SUPERTEX, INC.
To: SUPERTEX LLC
Reel/Frame 034682/0134 →