Multi-layered copper line structure of semiconductor device and method for forming the same

1. A multi-layered copper line structure of a semiconductor device, comprising:

a lower copper line formed above a lower structure of a semiconductor device;

an upper copper line formed above the lower copper line;

a via contact formed between the lower copper line and the upper copper line to electrically connect the lower copper line and the upper copper line; and

a dummy via contact formed adjacent the via contact, wherein the dummy via contact is connected to the upper copper line but is not connected to the lower copper line,

wherein the via contact is provided in plurality and the dummy via contact is provided in plurality between the via contacts, wherein the dummy via contacts are formed in a line parallel to a line of the upper copper line.

2. The multi-layered copper line structure according to claim 1 , further comprising:

a first interlayer insulating layer, formed above the lower structure of a semiconductor device, and in which the lower copper line is formed;

a second interlayer insulating layer, formed above the lower copper line, and in which the via contact is formed; and

a third interlayer insulating layer, formed above the second interlayer insulating layer, and in which the upper copper line is formed.

3. The multi-layered copper line structure according to claim 2 , wherein the first interlayer insulating layer, the second interlayer insulating layer, and the third interlayer insulating layer are formed of material having a dielectric constant of about 3.5 or less.

4. The multi-layered copper line structure according to claim 2 , wherein the dummy via contact is formed in the second interlayer insulating layer.

5. The multi-layered copper line structure according to claim 2 , wherein the dummy via contact is formed in the first interlayer insulating layer and the second interlayer insulating layer.

6. The multi-layered copper line structure according to claim 2 , further comprising

a diffusion barrier layer on the first interlayer insulating layer; and

a copper seed layer on the diffusion barrier layer.

7. The multi-layered copper line structure according to claim 1 , wherein the via contact is provided in plurality, and at least one dummy via contact is formed close to each of the via contacts while not being connected to the lower copper line.

8. The multi-layered copper line structure according to claim 1 , wherein the dummy via contact is further provided in plurality adjacent the via contact, wherein the dummy via contacts are formed in the line parallel to a line of the upper copper line and in the line perpendicular to the line of the copper line.

9. The multi-layered copper line structure according to claim 1 , wherein the dummy via contact is formed adjacent the via contact at a location spaced apart from the via contact by about 0.3 μm˜about 0.5 μm.

10. A method for forming a multi-layered copper line of a semiconductor device, comprising:

forming a first interlayer insulating layer above a lower structure;

forming a lower copper line within the first interlayer insulating layer;

forming a second interlayer insulating layer above the first interlayer insulating layer and the lower copper line;

forming at least one via contact and at least one dummy via contact within the second interlayer insulating layer;

forming a third interlayer insulating layer above the second interlayer insulating layer; and

forming an upper copper line within the third interlayer insulating layer,

wherein forming the at least one via contact and at least one dummy via contact within the second interlayer insulating layer, comprises:

forming a plurality of via contacts and a plurality of dummy contacts, wherein dummy via contacts are formed between via contacts in a line of the upper copper line.

11. The method according to claim 10 , wherein forming the lower copper line within the first interlayer insulating layer comprises:

depositing a diffusion barrier layer on the first interlayer insulating layer;

depositing a copper seed layer on the diffusion barrier layer; and

forming a first copper layer.

12. The method according to claim 11 , further comprising performing a thermal treatment after the forming the first copper layer.

13. The method according to claim 10 , wherein the at least one via contact is connected to the lower copper line, and the at least one dummy via contact is formed adjacent to the at least one via contact and within the second interlayer insulating layer and the first interlayer insulating layer.

14. The method according to claim 10 , wherein the upper copper line is formed contacting the at least one via contact and the at least one dummy via contact.

15. The method according to claim 10 , wherein forming the upper copper line within the third interlayer insulating layer, comprises:

depositing a diffusion barrier layer and a copper seed layer on the second interlayer insulating layer and the third interlayer insulating layer; and

forming a second copper layer,

wherein forming the second copper layer fills the at least one via contact, the at least one dummy via contact, and the upper copper line.

16. The method according to claim 15 , further comprising performing a thermal treatment after forming the second copper layer.

17. The method according to claim 10 , wherein the first interlayer insulating layer, the second interlayer insulating layer, and the third interlayer insulating layer are formed of material having a dielectric constant of about 3.5 or less.

18. The method according to claim 10 , wherein forming the at least one via contact and at least one dummy via contact within the second interlayer insulating layer, further comprises:

forming a second plurality of dummy contacts adjacent the at least one via contact, wherein the second plurality of dummy contacts adjacent the at least one via contact a formed in a line perpendicular to the line of the upper copper line.