Storage device and control method therefor
View Patent ↗The conductance of a first switch circuit (T 1 ) is periodically controlled in response to an error-amplification circuit (A 1 ) whereby electric power, stored in an inductance circuit (L 1 ) from INPUT VOLTAGE VIN, is released, through a rectifier circuit (D 1 ), to a memory cell array ( 11 ) for providing BIAS VOLTAGE VPP stepped up to a set voltage value. At this time, a voltage regulating section ( 13 ) acts on the error-amplification circuit (A 1 ) of the stepped up voltage supplying section ( 12 ) in response to LOCATIONAL INFORMATION AD about a memory cell as a voltage application target of BIAS VOLTAGE VPP and COUNTER INFORMATION COUNT, and directly regulates the voltage value of BIAS VOLTAGE VPP. Even for large storage capacity devices, it is possible to supply a bias voltage stepped up with a sufficient supply capability to the memory cell array ( 11 ). It is also possible to supply an optimum stepped up bias voltage by regulation of the set voltage depending on the position of a target memory cell, regardless of the number of target memory cells and their position.
1. A storage device comprising:
a memory cell array;
a boosted-voltage supplying section which supplies a bias voltage to the memory cell array, the bias voltage being generated by boosting an input voltage; and
a voltage regulating section which regulates a set voltage wherein the voltage regulating section sets a voltage value of the bias voltage in response to at least any one of a position in the memory cell array which is to be supplied with the bias voltage, and/or a number of times that the bias voltage is applied to the memory cell array, and a verify operation after application of the bias voltage which outputs a regulated voltage regulated in response to at least one of the set voltage and the bias voltage,
wherein the boosted-voltage supplying section comprises:
an error-amplification circuit which amplifies an error voltage with a value deviated from the set voltage of the bias voltage in response to the set voltage and/or the regulated voltage after regulation thereof;
an inductance circuit coupled between the input voltage and a first node;
a first switch circuit coupled between the first node and a reference voltage; and
a rectifier circuit coupled between the first node and the memory cell array, the rectifier circuit being energized in a direction from the first node to the memory cell array,
wherein the first switch circuit, or the first switch circuit and the rectifier circuit is periodically energized in response to operation of the error-amplification circuit.
2. The storage device in accordance with claim 1 , wherein the voltage regulating section regulates the bias voltage in response to address information corresponding to positional information related to the position of a memory cell in the memory cell array to which the bias voltage is to be supplied.
3. The storage device in accordance with claim 2 , wherein the voltage regulating section regulates the bias voltage in response to redundancy information associated with the memory cell instead of address information associated therewith when the memory cell is remedied.
4. The storage device in accordance with claim 3 , wherein the memory cell array includes a plurality of divided blocks, and
wherein the address information corresponds to the positional information identifying the plurality of divided blocks individually and the redundancy information includes the positional information identifying one of the plurality of divided blocks in which a redundant memory cell is located.
5. The storage device in accordance with claim 1 , wherein the voltage regulating section regulates the bias voltage in response to a number of times that the bias voltage is applied to the memory cell array, and/or counter information which instructs a verify operation after the application of the bias voltage.
6. The storage device in accordance with claim 5 , wherein the counter information is transmitted to a program/erase state machine which controls a program or an erase state.
7. The storage device in accordance with claim 1 , wherein the voltage regulating section regulates gain of the set voltage and/or the bias voltage to be supplied to the error-amplification circuit.
8. The storage device in accordance with claim 7 , wherein the set voltage and/or the bias voltage is divided and then supplied to the error-amplification circuit, and
wherein the voltage regulating section regulates a dividing ratio of the set voltage and/or the bias voltage.
9. The storage device in accordance with claim 1 further comprising a second switch circuit coupled between the rectifier circuit and the memory cell array, wherein the second switch circuit is energized when the bias voltage to be supplied to the memory cell array through the rectifier circuit is substantially equivalent to a predetermined voltage.
10. The storage device in accordance with claim 1 further comprising:
a first control section which energizes the first switch circuit when a load amount of the bias voltage set in response to the position in the memory cell array is less than or equal to a predetermined value; and
a second control section which energizes the first switch circuit when the load amount of the bias voltage set in response to the position in the memory cell array is greater than or equal to the predetermined value.
11. The storage device in accordance with claim 10 , wherein the predetermined value of the load amount is determined in response to a number of memory cells which are to be simultaneously supplied with the bias voltage.
12. The storage device in accordance with claim 10 , wherein the first control section is a VFM control section and the second control section is a PWM control section.
13. A method of controlling a storage device comprising the steps of:
regulating a set voltage of a bias voltage in response to at least any one of a position in a memory cell array which is to be supplied with the bias voltage, and/or a number of times that the bias voltage is applied to the memory cell array, and/or a verify operation after the application of the bias voltage which outputs a regulated voltage regulated in response to at least one of the set voltage and the bias voltage; and
managing the bias voltage in response to the set voltage by periodically storing power of an input voltage in an inductance circuit and then supplying the power to the memory cell array.
14. The control method in accordance with claim 13 , wherein the regulating step includes regulating the bias voltage in response to address information corresponding to positional information of the position of a memory cell in the memory cell array to which the bias voltage is to be supplied.
15. The control method in accordance with claim 14 , wherein the regulating step includes regulating the bias voltage in response to redundancy information instead of the address information when the memory cell is remedied.
16. The control method in accordance with claim 13 , wherein the regulating step includes regulating the bias voltage in response to a number of times that the bias voltage is applied to the memory cell array, and/or a verify operation after the application of the bias voltage.
17. The control method in accordance with claim 13 , wherein
the regulating step includes regulating a gain of the set voltage and/or the bias voltage; and
the bias voltage managing step includes amplifying an error voltage with a value deviated from the set voltage of the bias voltage in response to the set voltage and/or the regulated voltage, each having been regulated.
18. The control method in accordance with claim 13 further comprising the steps of:
storing power in the inductance circuit during a first cycle when a load amount of the bias voltage requested by the memory cell array is less than or equal to a predetermined value; and
storing the power in the inductance circuit during a second cycle when the load amount of the bias voltage requested by the memory cell array is greater than or equal to the predetermined value.
19. The control method in accordance with claim 18 , wherein the first cycle is determined in response to a VFM control and the second cycle is determined in response to a PWM control.