IP Library Granted Patent US 7,943,982
Granted Patent B2
US 7,943,982 · App. 11/444,216 · Granted May 17, 2011

Semiconductor device having laminated electronic conductor on bit line

Assignee: Spansion LLC
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Quick Facts
Patent No.
US 7,943,982
App. No.
11/444,216
Granted
May 17, 2011
Kind
B2
Abstract

There are provided a semiconductor device and a fabrication method therefor including an ONO film ( 18 ) formed on a semiconductor substrate ( 10 ), a word line ( 24 ) formed on the ONO film ( 18 ), a bit line ( 20 ) formed in the semiconductor substrate ( 10 ), and a conductive layer ( 32 ) that is in contact with the bit line ( 20 ), runs in a length direction of the bit line ( 20 ), and includes a polysilicon layer or a metal layer. In accordance with the present invention, a semiconductor device and a fabrication method therefor are provided wherein degradation of the writing and erasing characteristics and degradation of the transistor characteristics such as a junction leakage are suppressed, and the bit line resistance is decreased.

Claims (25)

1. A semiconductor device comprising:

an ONO film formed on a semiconductor substrate;

a word line formed on the ONO film;

a bit line formed in the semiconductor substrate; and

a conductive layer in contact with the bit line, the conductive layer overlying the semiconductor substrate and running in a direction of a length of the bit line, wherein the conductive layer runs substantially the entire length of the bit line, and wherein the conductive layer comprises either a polysilicon layer or a metal layer.

2. The semiconductor device as claimed in claim 1 , wherein the conductive layer is thicker than the ONO film.

3. The semiconductor device as claimed in claim 2 , wherein the bit line resistance may be lowered by increasing the thickness of the conductive layer.

4. The semiconductor device as claimed in claim 2 , wherein the bit line resistance may be lowered by increasing the thickness of the conductive layer relative to the ONO film.

5. The semiconductor device as claimed in claim 1 , wherein the word line is isolated from the conductive layer by at least a portion of a top oxide film provided in the ONO film.

6. The semiconductor device as claimed in claim 5 , wherein the word line and the conductive layer are isolated from each other by a top oxide film.

7. The semiconductor device as claimed in claim 1 , wherein the conductive layer is successively formed in a current-flowing direction.

8. The semiconductor device as claimed in claim 1 , wherein the conductive layer has a lower resistance than the bit line.

9. The semiconductor device as claimed in claim 1 , wherein the conductive layer underlies the word line.

10. A memory device comprising:

an ONO film formed on a semiconductor substrate;

a word line formed on the ONO film;

a bit line formed in the semiconductor substrate; and

a conductive layer in contact with the bit line and running substantially along a length of the bit line, wherein the conductive layer runs substantially the entire length of the bit line, wherein the conductive layer underlies the word line and overlies the semiconductor substrate, and wherein the conductive layer comprises either a polysilicon layer or a metal layer.

11. The memory device as claimed in claim 10 , wherein the conductive layer is thicker than the ONO film.

12. The memory device as claimed in claim 11 , wherein the bit line resistance may be lowered by increasing the thickness of the conductive layer.

13. The memory device as claimed in claim 11 , wherein the bit line resistance may be lowered by increasing the thickness of the conductive layer relative to the ONO film.

14. The memory device as claimed in claim 10 , wherein the word line is isolated from the conductive layer by at least a portion of a top oxide film provided in the ONO film.

15. The memory device as claimed in claim 14 , wherein the word line and the conductive layer are isolated from each other by a top oxide film.

16. The memory device as claimed in claim 10 , wherein the conductive layer is successively formed in a current-flowing direction.

17. The memory device as claimed in claim 10 , wherein the conductive layer has a lower resistance than the bit line.

Assignments (9)
CORRECTIVE ASSIGNMENT TO CORRECT THE 8647899 PREVIOUSLY RECORDED ON REEL 035240 FRAME 0429. ASSIGNOR(S) HEREBY CONFIRMS THE SECURITY INTERST. Recorded Nov 3, 2020
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 058002/0470 →
RELEASE OF SECURITY INTEREST Recorded Dec 19, 2019
From: MUFG UNION BANK, N.A.
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 051334/0633 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 11, 2019
From: CYPRESS SEMICONDUCTOR CORPORATION
To: LONGITUDE FLASH MEMORY SOLUTIONS LIMITED
Reel/Frame 051251/0787 →
ASSIGNMENT AND ASSUMPTION OF SECURITY INTEREST IN INTELLECTUAL PROPERTY Recorded Oct 28, 2019
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: MUFG UNION BANK, N.A.
Reel/Frame 050896/0366 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 2, 2015
From: SPANSION, LLC
To: CYPRESS SEMICONDUCTOR CORPORATION
Reel/Frame 036050/0174 →
SECURITY INTEREST Recorded Mar 21, 2015
From: CYPRESS SEMICONDUCTOR CORPORATION; SPANSION LLC
To: MORGAN STANLEY SENIOR FUNDING, INC.
Reel/Frame 035240/0429 →
RELEASE OF SECURITY INTEREST Recorded Mar 13, 2015
From: BARCLAYS BANK PLC
To: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY LLC
Reel/Frame 035201/0159 →
SECURITY AGREEMENT Recorded Jun 4, 2010
From: SPANSION LLC; SPANSION INC.; SPANSION TECHNOLOGY INC.; SPANSION TECHNOLOGY LLC
To: BARCLAYS BANK PLC
Reel/Frame 024522/0338 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Aug 23, 2006
From: FUJII, KENICHI; HIGASHI, MASAHIKO
To: SPANSION LLC
Reel/Frame 018168/0853 →
Continuity (2)
Continuation PCTJP2005009878 · May 30, 2005
Related Publication 20060278936A1 · Dec 14, 2006