IP Library Granted Patent US 8,581,380
Granted Patent B2
US 8,581,380 · App. 11/456,554 · Granted Nov 12, 2013

Integrated circuit packaging system with ultra-thin die

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Quick Facts
Patent No.
US 8,581,380
App. No.
11/456,554
Granted
Nov 12, 2013
Kind
B2
Abstract

An integrated circuit packaging system with ultra-thin die is provided including providing an ultra-thin integrated circuit stack, having a vertical sidewall contact, including providing a semiconductor wafer having an active side, forming a solder bump on the active side of the semiconductor wafer, forming a support layer over the solder bump and the active side of the semiconductor wafer, forming an ultra-thin wafer from the semiconductor wafer and singulating the ultra-thin integrated circuit stack for exposing the vertical sidewall contact, mounting the ultra-thin integrated circuit stack on a substrate, and coupling the substrate to the vertical sidewall contact.

Claims (65)

1. An integrated circuit package comprising:

a substrate having a substrate top and a substrate bottom;

a first ultra-thin integrated circuit attached to the substrate top, the first ultra-thin integrated circuit having a first contact pad with a first elliptical over-aligned bump bond pad attached thereon;

a second ultra-thin integrated circuit over the first ultra-thin integrated circuit, the second ultra-thin integrated circuit having a second contact pad with a second elliptical over-aligned bump bond pad attached thereon;

an epoxy molding compound operable to encapsulate the first ultra-thin integrated circuit and the first contact pad, and the second ultra-thin integrated circuit and the second contact pad, wherein a vertical sidewall of the epoxy molding compound exposes the first elliptical over-aligned bump bond pad and the second elliptical over-aligned bump bond pad;

a first electrical interconnect coupled for the first elliptical over-aligned bump bond pad through the vertical sidewall directly to the substrate top; and

a second electrical interconnect coupled from the second elliptical over-aligned bump bond pad through the vertical sidewall directly to the substrate top.

2. The package as claimed in claim 1 , wherein:

the first electrical interconnect is a first bond wire, and

the second electrical interconnect is a second bond wire.

3. The package as claimed in claim 1 , further comprising:

system interconnects attached to the substrate bottom.

4. The package as claimed in claim 3 , wherein the system interconnects include solder balls, solder columns or stud bumps.

5. An integrated circuit package comprising:

a first metalized substrate having a first metal side contact;

a second metalized substrate over the first metalized substrate, the second metalized substrate having a second metal side contact, wherein the second metal side contact and the first metal side contact have a staggered configuration;

a first ultra-thin integrated circuit stack mounted over the first metalized substrate and the second metalized substrate, wherein the first ultra-thin integrated circuit stack includes:

a first ultra-thin integrated circuit having a first contact pad with a first elliptical over-aligned bump pad attached thereon; and

an epoxy molding compound operable to encapsulate the first ultra-thin integrated circuit and the first contact pad, wherein a vertical sidewall of the epoxy molding compound exposes the first elliptical over-aligned bump bond pad; and

a first electrical interconnect coupled from the first ultra-thin integrated circuit through the vertical sidewall to at least one of:

the first metal side contact, and

the second metal side contact.

6. The package as claimed in claim 5 , wherein:

the second metalized substrate includes top metal contact, where the top metal contact and the second metal side contact and the first metal side contact have the staggered configuration; and

the first electrical interconnect is coupled from the first ultra-thin integrated circuit through the vertical sidewall to the top metal contact.

7. The package as claimed in claim 6 , further comprising:

a second ultra-thin integrated circuit stack mounted over the first ultra-thin integrated circuit stack, wherein the second ultra-thin integrated circuit stack includes:

a second ultra-thin integrated circuit having a second contact pad with a second elliptical over-aligned bump pad attached thereon; and

wherein the epoxy molding compound is operable to encapsulate the second ultra-thin integrated circuit and the second contact pad, wherein the vertical sidewall of the epoxy molding compound exposes the second elliptical over-aligned bump bond pad; and

a second electrical interconnect coupled from the second ultra-thin integrated circuit through the vertical sidewall to at least one of:

the first ultra-thin integrated circuit through the vertical sidewall,

the first metal side contact,

the second metal side contact, and

the top metal contact.

8. The package as claimed in claim 7 , further comprising:

an integrated circuit mounted over the second ultra-thin integrated circuit stack and the first ultra-thin integrated circuit stack, wherein the integrated circuit includes a bonding contact; and

a third electrical interconnect coupled from the bonding contact to at least one of:

the first ultra-thin integrated circuit through the vertical sidewall,

the second ultra-thin integrated circuit through the vertical sidewall,

the first metal side contact,

the second metal side contact, and

the top metal contact.

9. The package as claimed in claim 8 , wherein the first metal side contact is a first gold contact, the second metal side contact is a second gold contact, and the top metal contact is a third gold contact.

10. The package as claimed in claim 8 , wherein

the first electrical interconnect is a first bond wire,

the second electrical interconnect is a second bond wire, and

the third electrical interconnect is a third bond wire.

11. The package as claimed in claim 8 , further comprising:

system interconnects attached to the bottom of the first metalized substrate.

12. The package as claimed in claim 11 , wherein the system interconnects include solder balls, solder columns or stud bumps.

13. An integrated circuit package comprising:

a substrate having a substrate top and a substrate bottom;

a first ultra-thin integrated circuit attached to the substrate top, the first ultra-thin integrated circuit having a first contact pad with a first elliptical over-aligned bump bond pad attached thereon;

a second ultra-thin integrated circuit over the first ultra-thin integrated circuit, the second ultra-thin integrated circuit having a second contact pad with a second elliptical over-aligned bump bond pad attached thereon;

an epoxy molding compound operable to encapsulate the first ultra-thin integrated circuit and the first contact pad, and the second ultra-thin integrated circuit and the second contact pad,

wherein a first oblique cut surface of the epoxy molding compound exposes the first elliptical over-aligned bump bond pad, and

wherein a second oblique cut surface of the epoxy molding compound exposes the second elliptical over-aligned bump bond pad;

a first electrical interconnect coupled from the first elliptical over-aligned bump bond pad through the first oblique cut surface directly to the substrate top; and

a second electrical interconnect coupled from the second elliptical over-aligned bump bond pad through the second oblique cut surface directly to the substrate top.

14. The package as claimed in claim 13 , wherein:

the first electrical interconnect is a first bond wire, and

the second electrical interconnect is a second bond wire.

15. The package as claimed in claim 13 , further comprising:

system interconnects attached to the substrate bottom.

16. The package as claimed in claim 15 , wherein the system interconnects include solder balls, solder columns or stud bumps.

Assignments (4)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE>" TO "STATS CHIPPAC PTE. LTD" PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0219. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064803/0300 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →