Patent Assignment
Reel/Frame 064803/0300
Corrective Assignment to Correct the Correct the Spelling of Assignee's Name from "Stats Chippac Pte. Lte>" to "Stats Chippac Pte. Ltd" Previously Recorded at Reel: 038378 Frame: 0219. Assignor(S) Hereby Confirms the Assignment.
Recorded: 2023-09-01
Pages: 19
Assignor
STATS CHIPPAC LTD.
Executed: 2016-03-29
Assignee
STATS CHIPPAC PTE. LTD.
5 YISHUN STREET 23, SINGAPORE, SINGAPORE
Covered Properties
(54)
Ultra-Thin Wafer System and Method of Manufacture Thereof
Padless Die Support Integrated Circuit Package System
Integrated Circuit Packaging System with Ultra-Thin Die
Workpiece Displacement System
Dual-Die Package Structure Having Dies Externally and Simultaneously Connected via Bump Electrodes and Bond Wires
Integrated Circuit Package System with Bump Over Via
Integrated Circuit Package System Employing Multi-Package Module Techniques
Integrated Circuit Package System with Flex Bump
Integrated Circuit Package System with Wafer Scale Heat Slug
Flip Chip Interconnection System Having Solder Position Control Mechanism
Mock Bump System for Flip Chip Integrated Circuits
Mock Bump System for Flip Chip Integrated Circuits
Integrated Circuit Packaging System with an Interposer and Method of Manufacture Thereof
Integrated Circuit Packaging System with Through Silicon via Base and Method of Manufacture Thereof
Integrated Circuit Packaging System with Package-on-Package Stacking and Method of Manufacture Thereof
Stacked Integrated Circuit Package-in-Package System and Method of Manufacture Thereof
Integrated Circuit Packaging System with Encapsulated Connector and Method of Manufacture Thereof
Integrated Circuit Package System and Method of Manufacture Thereof
Semiconductor Device and Method of Forming Through Vias with Reflowed Conductive Material
Integrated Circuit Packaging System with Reinforced Encapsulant Having Embedded Interconnect and Method of Manufacture Thereof
Integrated Circuit Packaging System with Leadframe and Method of Manufacture Thereof
Integrated Circuit Package System with Integral Inner Lead and Paddle and Method of Manufacture Thereof
Semiconductor Device and Method of Forming Protective Layer Over Exposed Surfaces of Semiconductor Die
Semiconductor Device and Method of Forming Through Hole Vias in Die Extension Region Around Periphery of Die
Semiconductor Device and Method of Forming Protective Structure Around Semiconductor Die for Localized Planarization of Insulating Layer
Semiconductor Device and Method of Forming Multi-Layered Ubm with Intermediate Insulating Buffer Layer to Reduce Stress for Semiconductor Wafer
Semiconductor Device and Method of Forming Conductive THV and RDL on Opposite Sides of Semiconductor Die for RDL-to-RDL Bonding
Integrated Circuit Packaging System with Step Mold and Method of Manufacture Thereof
Integrated Circuit Packaging System with Interconnects and Method of Manufacture Thereof
Integrated Circuit Packaging System with Locking Interconnects and Method of Manufacture Thereof
Integrated Circuit Packaging System with Interconnect and Method of Manufacture Thereof
Integrated Circuit Packaging System with Interlock and Method of Manufacture Thereof
Integrated Circuit Protruding Pad Package System and Method for Manufacturing Thereof
Method of Manufacturing Integrated Circuit Packaging System with Support Structure
Integrated Circuit Packaging System with Support Structure and Method of Manufacture Thereof
Semiconductor Device and Method of Forming Interconnect Structure Over Seed Layer on Contact Pad of Semiconductor Die Without Undercutting Seed Layer Beneath Interconnect Structure
Integrated Circuit Package System with Laminate Base
Integrated Circuit Packaging System with Dual Side Mold and Method of Manufacture Thereof
Integrated Circuit System with Test Pads and Method of Manufacture Thereof
Semiconductor Device and Method of Forming Integrated Passive Device Over Semiconductor Die with Conductive Bridge and Fan-Out Redistribution Layer
Semiconductor Device and Method of Forming Thick Encapsulant for Stiffness with Recesses for Stress Relief in Fo-Wlcsp
Semiconductor Device and Method of Forming Vertical Interconnect Structure with Conductive Micro via Array for 3-D Fo-Wlcsp
Integrated Circuit Packaging System with Contacts and Method of Manufacture Thereof
Integrated Circuit Packaging System with Package-on-Package and Method of Manufacture Thereof
Semiconductor Device Having Conductive Vias in Peripheral Region Connecting Shielding Layer to Ground
Semiconductor Device and Method of Forming Non-Linear Interconnect Layer with Extended Length for Joint Reliability
Optical Semiconductor Device Having Pre-Molded Leadframe with Window and Method Therefor
Integrated Circuit Packaging System with Pad Connection and Method of Manufacture Thereof
Leadframe-Based Mold Array Package Heat Spreader and Fabrication Method Therefor
Integrated Circuit Packaging System with Grid-Array Mechanism and Method of Manufacture Thereof
Semiconductor Device and Method of Dual-Molding Die Formed on Opposite Sides of Build-Up Interconnect Structure
Semiconductor Device and Method for Forming Passive Circuit Elements With Through Silicon Vias to Backside Interconnect Structures
Package-On-Package System with Through Vias and Method of Manufacture Thereof
Solder Joint Flip Chip Interconnection
Patent:
44,608 →
Application:
13/756,905 →
Related Assignments
(5)
Other recorded transfers of the patents in this record — the chain of ownership.
Security Interest
Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
Release of Security Interest
Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
Assignment of Assignor's Interest
Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
Release of Security Interest
Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
Assignment of Assignor's Interest
Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →