IP Library Granted Patent US 8,623,702
Granted Patent B2
US 8,623,702 · App. 13/034,133 · Granted Jan 7, 2014

Semiconductor device and method of forming conductive THV and RDL on opposite sides of semiconductor die for RDL-to-RDL bonding

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Quick Facts
Patent No.
US 8,623,702
App. No.
13/034,133
Granted
Jan 7, 2014
Kind
B2
Abstract

A semiconductor device has a plurality of semiconductor die mounted to a carrier. An encapsulant is deposited over the carrier around a peripheral region of the semiconductor die. A plurality of vias is formed through the encapsulant. A first conductive layer is conformally applied over a sidewall of the vias to form conductive vias. A second conductive layer is formed over a first surface of the semiconductor die between the conductive vias and contact pads of the semiconductor die. The first and second conductive layers can be formed during the same manufacturing process. A third conductive layer is formed over a second surface of the semiconductor die opposite the first surface of the semiconductor die. The third conductive layer is electrically connected to the conductive vias. A plurality of semiconductor die is stacked and electrically connected through the conductive vias and second and third conductive layers.

Claims (88)

1. A method of making a semiconductor device, comprising:

providing a first carrier;

disposing a plurality of semiconductor die over the first carrier;

depositing a first encapsulant over the first carrier around a peripheral region of the plurality of semiconductor die;

forming a plurality of vias through the first encapsulant;

conformally applying a first conductive layer over a sidewall of the vias to form conductive vias with a surface of the conductive vias exposed to an interior of the vias following a contour of the sidewall of the vias;

forming a second conductive layer directly on the first encapsulant and a first surface of the plurality of semiconductor die between the conductive vias and contact pads of the plurality of semiconductor die;

providing a second carrier;

disposing a second surface of the plurality of semiconductor die opposite the first surface of the plurality of semiconductor die over the second carrier;

removing the first carrier;

forming a third conductive layer directly on the second surface of the plurality of semiconductor die and first encapsulant, the second and third conductive layers being electrically connected to the conductive vias; and

removing the second carrier.

2. The method of claim 1 , further including forming the first conductive layer and the second conductive layer during the same manufacturing process.

3. The method of claim 1 , further including singulating the plurality of semiconductor die through the conductive vias to form half conductive vias.

4. The method of claim 1 , further including:

stacking the plurality of semiconductor die; and

electrically connecting the plurality of semiconductor die through the conductive vias and the second and third conductive layers.

5. The method of claim 4 , further including:

mounting the plurality of semiconductor die to a substrate; and

depositing a second encapsulant over the plurality of semiconductor die and the substrate.

6. The method of claim 1 , further including:

disposing a no flow underfill material between a first and second semiconductor die; and

stacking the first and second semiconductor die.

7. A method of making a semiconductor device, comprising:

providing a first carrier;

disposing a plurality of semiconductor die over the first carrier;

depositing a first encapsulant over the first carrier around a peripheral region of the semiconductor die;

forming a plurality of vias through the first encapsulant;

conformally applying a first conductive layer over a sidewall of the vias to form conductive vias with a central portion of the conductive vias devoid of electrically conductive material;

forming a second conductive layer over the first encapsulant and a first surface of the plurality of semiconductor die between the conductive vias and contact pads of the plurality of semiconductor die;

providing a second carrier;

disposing a second surface of the semiconductor die opposite the first surface of the semiconductor die over the second carrier;

removing the first carrier;

forming a third conductive layer over the second surface of the plurality of semiconductor die and first encapsulant, the second and third conductive layers being electrically connected to the conductive vias; and

removing the second carrier.

8. The method of claim 7 , further including forming the first conductive layer and the second conductive layer during the same manufacturing process.

9. The method of claim 7 , further including:

stacking the plurality of semiconductor die; and

electrically connecting the plurality of semiconductor die through the conductive vias and the second and third conductive layers.

10. The method of claim 9 , further including:

mounting the plurality of semiconductor die to a substrate; and

depositing a second encapsulant over the plurality of semiconductor die and substrate.

11. The method of claim 7 , further including:

stacking a plurality of different size semiconductor die; and

electrically connecting the plurality of different size semiconductor die through the conductive vias and the second and third conductive layers.

12. The method of claim 7 , further including:

disposing an insulating material between a first and second semiconductor die; and

stacking the first and second semiconductor die.

13. The method of claim 7 , further including singulating the plurality of semiconductor die through the conductive vias to form half conductive vias.

14. A method of making a semiconductor device, comprising:

depositing a first encapsulant around a peripheral region of a semiconductor die;

forming a conductive via through the first encapsulant with a central portion of the conductive via devoid of electrically conductive material;

forming a first conductive layer over the first encapsulant and a first surface of the semiconductor die between the conductive via and a contact pad of the semiconductor die;

providing a carrier;

disposing a second surface of the semiconductor die opposite the first surface of the semiconductor die over the carrier;

forming a second conductive layer over the second surface of the semiconductor die and first encapsulant, the first and second conductive layers being electrically connected to the conductive via; and

removing the carrier.

15. The method of claim 14 , further including forming the conductive via and the first conductive layer during the same manufacturing process.

16. The method of claim 14 , further including:

stacking a plurality of semiconductor die; and

electrically connecting the plurality of semiconductor die through the conductive via and the first and second conductive layers.

17. The method of claim 16 , further including:

mounting the plurality of semiconductor die to a substrate; and

depositing a second encapsulant over the plurality of semiconductor die and the substrate.

18. The method of claim 14 , further including:

stacking a plurality of different size semiconductor die; and

electrically connecting the plurality of different size semiconductor die through the conductive via and the first and second conductive layers.

19. The method of claim 14 , further including:

disposing an insulating material between a first and second semiconductor die; and

stacking the first and second semiconductor die.

20. A method of making a semiconductor device, comprising:

depositing a first encapsulant around a peripheral region of a semiconductor die;

forming a conductive via through the first encapsulant with a central portion of the conductive via devoid of electrically conductive material;

forming a first conductive layer directly on the first encapsulant and a first surface of the semiconductor die between the conductive via and a contact pad of the semiconductor die; and

forming a second conductive layer directly on the first encapsulant and a second surface of the semiconductor die opposite the first surface of the semiconductor die, the second conductive layer being electrically connected to the conductive via.

21. The method of claim 20 , further including forming the conductive via and the first conductive layer during the same manufacturing process.

22. The method of claim 20 , further including:

stacking a plurality of semiconductor die; and

electrically connecting the plurality of semiconductor die through the conductive via and the first and second conductive layers.

23. The method of claim 22 , further including:

disposing the plurality of semiconductor die over a substrate; and

depositing a second encapsulant over the plurality of semiconductor die and the substrate.

24. The method of claim 20 , further including:

stacking a plurality of different size semiconductor die; and

electrically connecting the plurality of different size semiconductor die through the conductive via and the first and second conductive layers.

25. The method of claim 20 , further including:

disposing an insulating material between a first and second semiconductor die; and

stacking the first and second semiconductor die.

Assignments (6)
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE>" TO "STATS CHIPPAC PTE. LTD" PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0219. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064803/0300 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 18, 2019
From: STATS CHIPPAC PTE. LTD.
To: JCET SEMICONDUCTOR (SHAOXING) CO., LTD.
Reel/Frame 051365/0680 →
RELEASE OF SECURITY INTEREST Recorded Dec 13, 2019
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 051285/0318 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0219 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 24, 2011
From: PAGAILA, REZA A.
To: STATS CHIPPAC, LTD.
Reel/Frame 025859/0001 →