Semiconductor device and method of dual-molding die formed on opposite sides of build-up interconnect structure
View Patent ↗A semiconductor device has a first interconnect structure. A first semiconductor die has an active surface oriented towards and mounted to a first surface of the first interconnect structure. A first encapsulant is deposited over the first interconnect structure and first semiconductor die. A second semiconductor die has an active surface oriented towards and mounted to a second surface of the first interconnect structure opposite the first surface. A plurality of first conductive pillars is formed over the second surface of the first interconnect structure and around the second semiconductor die. A second encapsulant is deposited over the second semiconductor die and around the plurality of first conductive pillars. A second interconnect structure including a conductive layer and bumps are formed over the second encapsulant and electrically connect to the plurality of first conductive pillars and the first and second semiconductor die.
1. A method of making a semiconductor device, comprising:
providing a first semiconductor component;
depositing a first encapsulant over the first semiconductor component;
forming a first interconnect structure over the first semiconductor component;
mounting a second semiconductor component to the first interconnect structure;
depositing a second encapsulant over the second semiconductor component and first interconnect structure; and
forming a second interconnect structure over the second encapsulant.
2. The method of claim 1 , further including forming a plurality of conductive vias through the first encapsulant or second encapsulant.
3. The method of claim 2 , wherein the conductive vias extend from the first encapsulant or second encapsulant.
4. The method of claim 2 , wherein the conductive vias are recessed with respect to a surface of the first encapsulant or a surface of the second encapsulant.
5. The method of claim 1 , further including planarizing the first encapsulant or second encapsulant.
6. The method of claim 1 , wherein the first semiconductor component or second semiconductor component is a discrete semiconductor component.
7. A method of making a semiconductor device, comprising:
providing a first semiconductor component;
depositing a first encapsulant over the first semiconductor component;
forming a first interconnect structure over the first semiconductor component;
mounting a second semiconductor component to the first interconnect structure; and
depositing a second encapsulant over the second semiconductor component.
8. The method of claim 7 , further including forming a second interconnect structure over the second encapsulant.
9. The method of claim 7 , further including forming a second interconnect structure over the first encapsulant opposite the first interconnect structure.
10. The method of claim 7 , further including forming a conductive via through the first encapsulant or second encapsulant.
11. The method of claim 10 , wherein the conductive via extends from the first encapsulant or second encapsulant.
12. The method of claim 10 , wherein the conductive via is recessed with respect to a surface of the first encapsulant or a surface of the second encapsulant.
13. The method of claim 7 , further including forming a shielding layer over the first encapsulant or second semiconductor component.
14. A method of making a semiconductor device, comprising:
providing a first semiconductor component;
depositing a first encapsulant over the first semiconductor component;
forming a first interconnect structure over the first semiconductor component; and
mounting a second semiconductor component to the first interconnect structure.
15. The method of claim 14 , further including depositing a second encapsulant over the second semiconductor component.
16. The method of claim 15 , further including forming a second interconnect structure over the second encapsulant.
17. The method of claim 16 , further including forming a second interconnect structure over the first encapsulant opposite the first interconnect structure.
18. The method of claim 15 , further including planarizing the first encapsulant or second encapsulant.
19. The method of claim 15 , further including forming a conductive via through the first encapsulant or second encapsulant.
20. The method of claim 14 , further including forming a shielding layer over the first encapsulant or second semiconductor component.
21. A semiconductor device, comprising:
a first semiconductor component;
a first encapsulant deposited over the first semiconductor component;
a first interconnect structure formed over the first semiconductor component; and
a second semiconductor component mounted to the first interconnect structure.
22. The semiconductor device of claim 21 , further including a second encapsulant deposited over the second semiconductor component.
23. The semiconductor device of claim 22 , further including a second interconnect structure formed over the second encapsulant or the first encapsulant opposite the first interconnect structure.
24. The semiconductor device of claim 22 , further including a conductive via formed through the first encapsulant or second encapsulant.
25. The semiconductor device of claim 21 , further including a shielding layer formed over the first encapsulant or second semiconductor component.