Package-on-package system with through vias and method of manufacture thereof

1. A method of manufacture of a package-on-package system comprising:

providing a substrate connection;

attaching a semiconductor die to the substrate connection using an adhesive, with the substrate connection affixed directly by the adhesive;

forming an encapsulant around the semiconductor die to have a bottom exposed surface coplanar with a bottom surface of the substrate connection and to have a top exposed surface with through openings extending therefrom through the bottom exposed surface;

creating through vias by applying solder into the through openings, the through vias coplanar with the bottom exposed surface of the encapsulant and coplanar with the top exposed surface of the encapsulant, and wherein providing the substrate connection includes supporting the substrate connection with a package carrier having the substrate connection there through.

2. The method as claimed in claim 1 wherein forming the encapsulant includes creating through openings located on one side of the substrate connection.

3. The method as claimed in claim 1 wherein attaching the semiconductor die includes encapsulating a segment of the substrate connection with the adhesive and having the bottom surface of the substrate connection exposed from the adhesive.

4. The method as claimed in claim 1 wherein providing the substrate connection includes providing dummy patterns incorporated with the substrate connection.

5. A method of manufacture of a package-on-package system comprising:

providing a package substrate including a package carrier and a substrate connection;

attaching a semiconductor die to the package substrate with an adhesive, with the adhesive directly contacting the substrate connection;

connecting the semiconductor die to the substrate connection in the package substrate using electrical interconnects;

molding an encapsulant around the semiconductor die using a mold with pins to have a bottom exposed surface coplanar with a bottom surface of the substrate connection and to have a top exposed surface, wherein the pins define through openings extending from the top exposed surface through the bottom exposed surface;

removing the package carrier of the package substrate; and

creating through vias by applying solder through a stencil plate with openings aligned to the through openings, the through vias coplanar with the bottom exposed surface of the encapsulant and coplanar with the top exposed surface of the encapsulant.

6. The method as claimed in claim 5 wherein molding the encapsulant including creating through openings located on either side of the substrate connection.

7. The method as claimed in claim 5 wherein:

attaching the semiconductor die includes encapsulating a segment of the substrate connection with the adhesive and having the bottom surface of the substrate connection exposed from the adhesive; and

forming the encapsulant includes encapsulating a remaining segment of the substrate connection with the encapsulant directly contacting the remaining segment of the substrate connection and the bottom surface of the substrate connection exposed from the encapsulant.

8. The method as claimed in claim 5 wherein providing the package substrate includes incorporating dummy patterns with the package carrier.

9. The method as claimed in claim 5 wherein molding the encapsulant includes formed a substrate-less package body.