Semiconductor device and method of forming vertical interconnect structure with conductive micro via array for 3-D Fo-WLCSP
View Patent ↗A semiconductor device has a semiconductor die. An encapsulant is formed over the semiconductor die. A conductive micro via array is formed over the encapsulant outside a footprint of the semiconductor die. A first through-mold-hole having a step-through-hole structure is formed through the encapsulant to expose the conductive micro via array. In one embodiment, forming the conductive micro via array further includes forming an insulating layer over the encapsulant and the semiconductor die, forming a micro via array through the insulating layer outside the footprint of the semiconductor die, and forming a conductive layer over the insulating layer. In another embodiment, forming the conductive micro via array further includes forming a conductive ring. In another embodiment, an insulating layer is formed over the semiconductor die for structural support, a build-up interconnect structure is formed over the semiconductor die, and a conductive interconnect structure is formed within the first through-mold-hole.
1. A method of making a semiconductor device, comprising:
providing a semiconductor die;
forming an encapsulant over the semiconductor die; and
forming a first through-mold-hole (TMH) through the encapsulant and including a step-through-hole structure.
2. The method of claim 1 , further including forming a conductive micro via array over the encapsulant outside a footprint of the semiconductor die.
3. The method of claim 2 , wherein forming the conductive micro via array further includes:
forming an insulating layer over the encapsulant and the semiconductor die;
forming a micro via array through the insulating layer outside the footprint of the semiconductor die; and
forming a conductive layer over the insulating layer.
4. The method of claim 2 , wherein forming the conductive micro via array further includes forming a conductive ring.
5. The method of claim 2 , wherein forming the first TMH further includes:
forming a second TMH partially through the encapsulant to a recessed surface of the encapsulant; and
forming a third TMH through the encapsulant within a footprint of the second TMH having a cross-sectional width less than a cross-sectional width of the second TMH and extending from the recessed surface of the encapsulant to the conductive micro via array.
6. The method of claim 1 , further including forming a conductive interconnect structure within the first TMH.
7. The method of claim 1 , further including forming a build-up interconnect structure over the semiconductor die.
8. A semiconductor device, comprising:
a semiconductor die;
an encapsulant formed over the semiconductor die;
a conductive micro via array formed over the semiconductor die and the encapsulant outside a footprint of the semiconductor die; and
a first through-mold-hole (TMH) having a step-through-hole structure formed through the encapsulant to expose the conductive micro via array.
9. The semiconductor device of claim 8 , further including:
an insulating layer formed over the semiconductor die and the encapsulant;
a micro via array formed through the insulating layer outside the footprint of the semiconductor die; and
a conductive layer formed over the insulating layer.
10. The semiconductor device of claim 8 , wherein the conductive micro via array further includes a conductive ring.
11. The semiconductor device of claim 8 , wherein the first TMH further includes:
a second TMH formed partially through the encapsulant to a recessed surface of the encapsulant; and
a third TMH formed through the encapsulant within a footprint of the second TMH having a cross-sectional width less than a cross-sectional width of the second TMH and extending from the recessed surface of the encapsulant to the conductive micro via array.
12. The semiconductor device of claim 8 , further including a build-up interconnect structure formed over the semiconductor die.
13. A semiconductor device, comprising:
a semiconductor die;
an encapsulant formed over the semiconductor die; and
a conductive micro via array including a plurality of conductive vias formed over the encapsulant and outside a footprint of the semiconductor die.
14. The semiconductor device of claim 13 , further including a first through-mold-hole (TMH) comprising a step-through-hole structure and formed through the encapsulant to expose the conductive micro via array.
15. The semiconductor device of claim 14 , wherein the first TMH further includes:
a second TMH formed partially through the encapsulant to a recessed surface of the encapsulant; and
a third TMH formed through the encapsulant and within a footprint of the second TMH, the third TMH comprising a cross-sectional width less than a cross-sectional width of the second TMH and extending from the recessed surface of the encapsulant to the conductive micro via array.
16. The semiconductor device of claim 14 , further including a conductive interconnect structure formed within the first TMH.
17. The semiconductor device of claim 13 , further including:
an insulating layer formed over the encapsulant and the semiconductor die;
a micro via array formed through the insulating layer and outside the footprint of the semiconductor die; and
a conductive layer formed over the insulating layer.
18. The semiconductor device of claim 17 , wherein the insulating layer further includes a polymer composite including glass fiber.
19. A semiconductor device, comprising:
a semiconductor die;
an encapsulant formed over the semiconductor die; and
a first through-mold-hole (TMH) formed through the encapsulant and including a step-through-hole structure.
20. The semiconductor device of claim 19 , further including:
an insulating layer formed over the encapsulant and the semiconductor die;
a micro via array formed through the insulating layer and outside a footprint of the semiconductor die; and
a conductive layer formed over the insulating layer.
21. The semiconductor device of claim 20 , wherein the insulating layer further includes a polymer composite including glass fiber.
22. The semiconductor device of claim 19 , wherein a conductive micro via array is formed over the encapsulant.
23. The semiconductor device of claim 22 , wherein the conductive micro via array further includes a conductive ring.
24. The semiconductor device of claim 13 , further including a second insulating layer formed over the conductive micro via array and including a polymer composite comprising glass fiber or woven glass.
25. The semiconductor device of claim 20 , further including a second insulating layer formed over the conductive layer and including a polymer composite comprising glass fiber or woven glass.
26. A semiconductor device, comprising:
a semiconductor die;
an encapsulant formed over the semiconductor die;
an insulating layer formed over the encapsulant; and
a conductive micro via array formed through the insulating layer.
27. The semiconductor device of claim 26 , further including a second insulating layer formed over the conductive micro via array and including a polymer composite comprising glass fiber or woven glass.
28. The semiconductor device of claim 26 , wherein the conductive micro via array further includes a conductive ring.
29. The semiconductor device of claim 26 , wherein the insulating layer further includes a polymer composite including glass fiber.
30. The semiconductor device of claim 26 , further including a first through-mold-hole (TMH) comprising a step-through-hole structure and formed through the encapsulant to expose the conductive micro via array.