Integrated circuit package system employing multi-package module techniques
View Patent ↗An integrated circuit package system that includes: providing a first package including a first package first device and a first package second device both adjacent a first package substrate; and mounting and electrically interconnecting a second package over an electrical interconnect array formed on a substrate of the first package second device.
1. A method of manufacture of an integrated circuit package system comprising:
providing a package substrate;
forming a first package over the package substrate, the first package including:
a first device having a first die and a second die, the first die being closer to the package substrate,
a second device having an encapsulation material and a device substrate, the encapsulation material being closer to the package substrate,
wherein the first device is adjacent the second device such that the second die of the first device abuts the device substrate of the second device;
forming an electrical interconnect array on the device substrate; and
mounting and electrically interconnecting a second package over the electrical interconnect array.
2. The method as claimed in claim 1 wherein:
forming the first package over the package substrate includes the second device being an inverted chip scale package with a land grid array.
3. The method as claimed in claim 1 wherein:
mounting and electrically interconnecting the second package includes electrically interconnecting the second package with a ball grid array.
4. The method as claimed in claim 1 further comprising:
forming an electrical connection between the second die of the first device and the device substrate of the second device.
5. A method of manufacture of an integrated circuit package system comprising:
providing a package substrate;
forming a first package over the package substrate, the first package including
an interior device having a first die and a second die, the first die being closer to the package substrate,
a first device having a first encapsulation material and a first device substrate, the first encapsulation material being closer to the package substrate,
a second device having a second encapsulation material and a second device substrate, the second encapsulation material being closer to the package substrate,
wherein the interior device is situated between the first device and the second device such that the second die of the interior device abuts the first device substrate of the first device and the second device substrate of the second device,
mounting and electrically interconnecting a second package directly onto the first device; and
mounting and electrically interconnecting a third package directly onto the second device.
6. The method as claimed in claim 5 wherein:
mounting and electrically interconnecting the second package includes mounting the second package onto the first device substrate of the first device; and
mounting and electrically interconnecting the third package includes mounting the third package onto the second device substrate of the second device.
7. The method as claimed in claim 5 further comprising:
forming an electrical connection between the second die of the interior device and the first device substrate of the first device and the second device substrate of the second device.
8. The method as claimed in claim 5 further comprising:
configuring each of the second package and the third package to include a passive device and a flip-chip device.
9. The method as claimed in claim 5 wherein:
mounting and electrically interconnecting the second package and mounting and electrically interconnecting the third package includes mounting each of the second package and the third package with a center ball grid array.
10. An integrated circuit package system comprising:
a package substrate;
a first package over the package substrate, the first package including:
a first device having a first die and a second die, the first die being closer to the package substrate,
a second device having an encapsulation material and a device substrate, the encapsulation material being closer to the package substrate,
wherein the first device is adjacent the second device such that the second die of the first device abuts the device substrate of the second device; and
a second package over an electrical interconnect array formed on the device substrate.
11. The system as claimed in claim 10 wherein:
the second device includes an inverted chip scale package.
12. The system as claimed in claim 10 wherein:
the electrical interconnect array formed on the device substrate of the second device includes a land grid array.
13. The system as claimed in claim 10 wherein:
the second package is electrically connected to the second device by a ball grid array.
14. The system as claimed in claim 10 further comprising:
an electrical connection between the second die and the device substrate of the second device.
15. The system as claimed in claim 10 wherein:
the integrated circuit package system includes a combination of processor devices and memory devices.
16. The system as claimed in claim 10 further comprising:
a third device adjacent the first device, the third device having a device substrate, wherein the second die of first device abuts the device substrate of the third device; and
a third package over an electrical interconnect array formed on the device substrate of the third device.
17. The system as claimed in claim 16 further comprising:
an electrical connection between the second die of the first device and the device substrate of the second device and the device substrate of the third device.
18. The system as claimed in claim 16 wherein:
each of the second package and the third package includes a passive device and a flip-chip device.