Integrated circuit package system with bump over via
View Patent ↗An integrated circuit package system includes a substrate, forming a resist layer having an elongated recess over the substrate, forming a via in the substrate below the elongated recess, and forming an elongated bump in the elongated recess over the via.
1. A method for manufacture of an integrated circuit package system comprising:
providing a substrate having a lower layer trace;
forming a resist layer having an elongated recess over the substrate;
forming a via in the substrate below the elongated recess and in the lower layer trace; and
forming an elongated bump pad in the elongated recess over the via, the elongated bump pad having a rounded, elongated shape with a top length greater than a top width.
2. The method as claimed in claim 1 wherein forming the via includes forming an elongated via.
3. The method as claimed in claim 1 wherein forming the via includes forming a single via.
4. The method as claimed in claim 1 wherein forming the via includes plating the via.
5. The method as claimed in claim 1 wherein forming the via includes filling the via.
6. A method of manufacture of an integrated circuit package system comprising:
providing a substrate having a lower layer trace and a top layer trace;
forming a resist layer having an elongated recess over the lower layer trace;
forming a via in the substrate below the elongated recess in the lower layer trace and in the top layer trace;
applying a conductive material over the via; and
forming an elongated bump pad in the elongated recess over the via and the lower layer trace, the elongated bump pad having a rounded, elongated shape with a top length greater than a top width.
7. The method as claimed in claim 6 wherein forming the via includes forming an elongated via in a dielectric layer.
8. The method as claimed in claim 6 wherein forming the via includes forming a single via in a dielectric layer.
9. The method as claimed in claim 6 wherein applying the conductive material includes plating the via with the conductive material.
10. The method as claimed in claim 6 wherein applying the conductive material includes filling the via with the conductive material.
11. An integrated circuit package system comprising:
a substrate having a lower layer trace;
a resist layer having an elongated recess over the substrate;
a via in the substrate below the elongated recess and in the lower layer trace; and
an elongated bump pad in the elongated recess over the via, the elongated bump pad having a rounded, elongated shape with a top length greater than a top width.
12. The system as claimed in claim 11 wherein the via is an elongated via.
13. The system as claimed in claim 11 wherein the via is a single via.
14. The system as claimed in claim 11 wherein the via is the via plated.
15. The system as claimed in claim 11 wherein via is the via filled.
16. The system as claimed in claim 11 wherein:
the substrate has a top layer trace;
the resist layer has the elongated recess over the top layer trace;
the via is in the substrate below the elongated recess in the lower layer trace and in the top layer trace;
the elongated bump is in the elongated recess over the via and the lower trace; and
further comprising:
applying a conductive material over the via.
17. The system as claimed in claim 16 wherein the via is an elongated via in a dielectric layer.
18. The system as claimed in claim 16 wherein the via is a single via in a dielectric layer.
19. The system as claimed in claim 16 wherein the conductive material includes the via plated with the conductive material.
20. The system as claimed in claim 16 wherein the conductive material includes the via filled with the conductive material.