IP Library Granted Patent US 8,633,058
Granted Patent B2
US 8,633,058 · App. 13/052,590 · Granted Jan 21, 2014

Integrated circuit packaging system with step mold and method of manufacture thereof

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Quick Facts
Patent No.
US 8,633,058
App. No.
13/052,590
Granted
Jan 21, 2014
Kind
B2
Abstract

A method of manufacture of an integrated circuit packaging system includes: providing a substrate; connecting an integrated circuit die to the substrate, with the integrated circuit die having peripheral sides; molding a step mold covering one of the peripheral sides; attaching an intermediate die directly over the integrated circuit die, offset to one of the peripheral sides adjacent to the step mold; and directly connecting the intermediate die to the substrate.

Claims (41)

1. A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate;

attaching an integrated circuit die to the substrate, the integrated circuit die having peripheral sides;

connecting the integrated circuit die to the substrate with a first bond wire, the first bond wire disposed about one of the peripheral sides;

molding a step mold covering one of the peripheral sides and the first bond wire;

attaching an intermediate die directly over the integrated circuit die, offset to one of the peripheral sides adjacent to the step mold;

directly connecting the intermediate die to the substrate with a second bond wire; and

encapsulating the intermediate die, the integrated circuit die, the step mold, the second bond wire, and the substrate with an encapsulation, the encapsulation not contacting the first bond wire.

2. The method as claimed in claim 1 wherein:

molding the step mold includes exposing the peripheral sides adjacent to the step mold; and

attaching the intermediate die includes attaching the intermediate die offset to one of the peripheral sides exposed by the step mold.

3. The method as claimed in claim 1 further comprising directly connecting the intermediate die to the integrated circuit die.

4. A method of manufacture of an integrated circuit packaging system comprising:

providing a substrate;

attaching an integrated circuit die to the substrate, the integrated circuit die having peripheral sides

connecting the integrated circuit die to the substrate with a bond wire, the bond wire disposed about one of the peripheral sides;

molding a step mold covering one of the peripheral sides and encapsulating the bond wire;

attaching an intermediate die directly over the integrated circuit die, offset to one of the peripheral sides adjacent to the step mold;

directly connecting the intermediate die to the substrate with an intermediate bond wire;

attaching a top die to the step mold and directly over the integrated circuit die and the intermediate die;

connecting the top die to the substrate with a top bond wire; and

encapsulating the top die, the intermediate die, the integrated circuit die, the step mold, the top bond wire, the intermediate bond wire, and the substrate with an encapsulation, the encapsulation not contacting the bond wire.

5. The method as claimed in claim 4 wherein attaching the intermediate die includes attaching a flip chip.

6. The method as claimed in claim 4 wherein attaching the intermediate die includes attaching a stack packaging.

7. An integrated circuit packaging system comprising:

a substrate;

an integrated circuit die attached to the substrate, the integrated circuit die having peripheral sides;

a bond wire operable to connect the integrated circuit die to the substrate, the bond wire disposed about one of the peripheral sides;

a step mold covering one of the peripheral sides and the bond wire;

an intermediate die attached directly over the integrated circuit die, offset to one of the peripheral sides adjacent to the step mold;

an intermediate bond wire operable to connect the intermediate die directly to the substrate; and

an encapsulation configured to encapsulate the intermediate die, the integrated circuit die, the step mold, the intermediate bond wire, and the substrate, the encapsulation not contacting the bond wire.

8. The system as claimed in claim 7 wherein:

the step mold exposes the peripheral sides adjacent to the step mold; and

the intermediate die is attached offset to one of the peripheral sides exposed by the step mold.

9. The system as claimed in claim 7 wherein the intermediate bond-wire is directly connected to the intermediate die and the integrated circuit die.

10. The system as claimed in claim 7 further comprising:

a top die attached to the step mold and directly over the integrated circuit die and the intermediate die;

a top bond wire operable to connect the top die directly to the substrate;

the encapsulation further configured to encapsulate the top die and the top bond wire.

11. The system as claimed in claim 10 wherein the intermediate die is a stack packaging.

Assignments (6)
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 3, 2025
From: STATS CHIPPAC PTE. LTD.
To: STATS CHIPPAC MANAGEMENT PTE. LTD.
Reel/Frame 072788/0917 →
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE>" TO "STATS CHIPPAC PTE. LTD" PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0219. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064803/0300 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0219 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Apr 1, 2011
From: CHOI, DAESIK; HA, JONG-WOO; KIM, SEUNG WON
To: STATS CHIPPAC LTD.
Reel/Frame 026063/0687 →