IP Library Granted Patent US 8,642,381
Granted Patent B2
US 8,642,381 · App. 12/837,562 · Granted Feb 4, 2014

Semiconductor device and method of forming protective layer over exposed surfaces of semiconductor die

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Quick Facts
Patent No.
US 8,642,381
App. No.
12/837,562
Granted
Feb 4, 2014
Kind
B2
Abstract

A semiconductor wafer has a plurality of first semiconductor die. A second semiconductor die is mounted to the first semiconductor die. A shielding layer is formed between the first and second semiconductor die. An electrical interconnect, such as conductive pillar, bump, or bond wire, is formed between the first and second semiconductor die. A conductive TSV can be formed through the first and second semiconductor die. An encapsulant is deposited over the first and second semiconductor die and electrical interconnect. A heat sink is formed over the second semiconductor die. An interconnect structure, such as a bump, can be formed over the second semiconductor die. A portion of a backside of the first semiconductor die is removed. A protective layer is formed over exposed surfaces of the first semiconductor die. The protective layer covers the exposed backside and sidewalls of the first semiconductor die.

Claims (52)

1. A method of making a semiconductor device, comprising:

providing a semiconductor wafer including a plurality of first semiconductor dies;

forming a plurality of conductive pillars over the semiconductor wafer;

disposing a second semiconductor die between the conductive pillars and over the first semiconductor dies;

depositing an encapsulant over the first and second semiconductor dies and conductive pillars;

removing a portion of a backside of the second semiconductor die and encapsulant to expose the conductive pillars;

forming an interconnect structure over the backside of the second semiconductor die, encapsulant, and conductive pillars;

disposing the semiconductor wafer over a temporary carrier with the interconnect structure oriented toward the temporary carrier;

removing a portion of a backside of the semiconductor wafer;

singulating the semiconductor wafer to the encapsulant;

forming a protective layer over a plurality of exposed surfaces of the first semiconductor dies;

removing the temporary carrier; and

singulating the semiconductor wafer into individual semiconductor devices.

2. The method of claim 1 , wherein the protective layer covers an exposed backside and exposed sidewalls of the first semiconductor dies.

3. The method of claim 1 , further including forming a conductive via through the first semiconductor dies.

4. The method of claim 1 , further including forming a conductive via through the second semiconductor die.

5. The method of claim 1 , further including applying penetrable tape to the temporary carrier for mounting the interconnect structure.

6. A method of making a semiconductor device, comprising:

providing a semiconductor wafer including a first semiconductor die;

disposing a second semiconductor die over the first semiconductor die;

forming an electrical interconnect between the first and second semiconductor die;

depositing an encapsulant over the first and second semiconductor die and electrical interconnect;

removing a portion of the first semiconductor die to expose sidewalls of the first semiconductor die; and

forming a protective layer over the sidewalls of the first semiconductor die and extending to the encapsulant.

7. The method of claim 6 , wherein the protective layer covers a backside and the sidewalls of the first semiconductor die.

8. The method of claim 6 , wherein the electrical interconnect includes a conductive pillar, bond wire, or bump.

9. The method of claim 6 , further including forming an interconnect structure over the second semiconductor die.

10. The method of claim 9 , wherein the interconnect structure includes a bump.

11. The method of claim 6 , further including removing a portion of a backside of the first semiconductor die prior to forming the protective layer.

12. The method of claim 6 , further including forming a shielding layer between the first and second semiconductor die.

13. The method of claim 6 , further including forming a heat sink over the second semiconductor die.

14. A method of making a semiconductor device, comprising:

providing a first semiconductor die;

disposing a second semiconductor die over the first semiconductor die;

forming an electrical interconnect between the first and second semiconductor die;

depositing an encapsulant over the first and second semiconductor die;

removing a portion of the first semiconductor die to expose surfaces of the first semiconductor die; and

forming a protective layer over the exposed surfaces of the first semiconductor die.

15. The method of claim 14 , wherein the exposed surfaces of the first semiconductor die include a backside and sidewalls of the first semiconductor die.

16. The method of claim 14 , wherein the electrical interconnect includes a conductive pillar, bond wire, or bump.

17. The method of claim 14 , further including forming a shielding layer between the first and second semiconductor die.

18. The method of claim 14 , further including forming a heat sink over the second semiconductor die.

19. The method of claim 14 , further including forming an interconnect structure over the second semiconductor die.

20. A method of making a semiconductor device, comprising:

forming an interconnect structure over a first semiconductor die;

disposing a second semiconductor die over the interconnect structure and first semiconductor die;

depositing an encapsulant over the first and second semiconductor die; and

forming a protective layer over an exposed surface of the first semiconductor die and extending to the encapsulant.

21. The method of claim 20 , wherein the protective layer covers an exposed backside and exposed sidewalls of the first semiconductor die.

22. The method of claim 20 , wherein the interconnect structure includes a conductive pillar, bond wire, or bump.

23. The method of claim 20 , further including forming a shielding layer between the first and second semiconductor die.

24. The method of claim 20 , further including forming a heat sink over the second semiconductor die.

Assignments (7)
CORRECTIVE ASSIGNMENT TO CORRECT THE CORRECT THE SPELLING OF ASSIGNEE'S NAME FROM "STATS CHIPPAC PTE. LTE>" TO "STATS CHIPPAC PTE. LTD" PREVIOUSLY RECORDED AT REEL: 038378 FRAME: 0219. ASSIGNOR(S) HEREBY CONFIRMS THE ASSIGNMENT. Recorded Sep 1, 2023
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTD.
Reel/Frame 064803/0300 →
RELEASE OF SECURITY INTEREST Recorded Jun 17, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 053476/0094 →
RELEASE OF SECURITY INTEREST Recorded Jun 5, 2020
From: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
To: STATS CHIPPAC, INC.; STATS CHIPPAC PTE. LTD. FORMERLY KNOWN AS STATS CHIPPAC LTD.
Reel/Frame 052850/0237 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0219 →
CHANGE OF NAME Recorded Apr 7, 2016
From: STATS CHIPPAC LTD.
To: STATS CHIPPAC PTE. LTE.
Reel/Frame 038378/0427 →
SECURITY INTEREST Recorded Aug 6, 2015
From: STATS CHIPPAC, INC.; STATS CHIPPAC LTD.
To: CITICORP INTERNATIONAL LIMITED, AS COMMON SECURITY AGENT
Reel/Frame 036288/0748 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jul 16, 2010
From: PAGAILA, REZA A.; CHOI, DAESIK; KOO, JUN MO
To: STATS CHIPPAC, LTD.
Reel/Frame 024695/0195 →