Enhanced method of optimizing multiplex structures and multiplex control structures in RTL code
View Patent ↗A method and computer program are disclosed for optimizing RTL code for an integrated circuit design that include steps of method of optimizing register transfer level code for an integrated circuit design comprising steps of receiving as input a first register transfer level code for the integrated circuit design and receiving as input criteria defining a critical multiplex structure. The first register transfer level code is analyzed to identify multiplex structures in the first register transfer level code. Each of the multiplex structures identified in the first register transfer level code is compared to the criteria defining a critical multiplex structure. Each of the multiplex structures identified in the first register transfer level code that satisfy the criteria defining a critical multiplex structure is entered in a list of critical multiplex structures. The list of critical multiplex structures is generated as output.
1. A method of optimizing register transfer level code for an integrated circuit design by a computer system comprising steps of:
(a) receiving as input of the computer system a first register transfer level code for the integrated circuit design;
(b) receiving as input criteria defining a critical multiplex structure;
(c) analyzing the first register transfer level code to identify multiplex structures in the first register transfer level code;
(d) comparing each of the multiplex structures identified in the first register transfer level code to the criteria defining a critical multiplex structure;
(e) including each of the multiplex structures identified in the first register transfer level code that satisfy the criteria defining a critical multiplex structure in a list of critical multiplex structures; and
(f) generating as output the list of critical multiplex structures.
2. The method of claim 1 further comprising a step of manually entering a multiplex structure in the list of critical multiplex structures.
3. The method of claim 1 further comprising a step of replacing each of the multiplex structures in the list of critical multiplex structures with corresponding noncritical multiplex structures.
4. The method of claim 3 further comprising a step of generating as output a second register transfer level code for the integrated circuit design with the corresponding non-critical multiplex structures.
5. The method of claim 1 further comprising including a variable and a threshold value for each variable in the criteria defining a critical multiplex structure.
6. The method of claim 5 further comprising including a variable in the criteria defining a critical multiplex structure for at least one of a number of buses, a number of signals per bus, a total number of signals, a number of register bank sources, a number of memory sources, a number of flip-flops, a number of start points, and a number of endpoints.
7. The method of claim 5 further comprising weighting the variable by a variable function of a priority value assigned to the variable.
8. A method of optimizing register transfer level code for an integrated circuit design by a computer system comprising steps of:
(a) receiving as input of the computer system a first register transfer level code for the integrated circuit design;
(b) receiving as input criteria defining a critical multiplex control structure;
(c) analyzing the first register transfer level code to identify multiplex control structures in the first register transfer level code;
(d) comparing each of the multiplex control structures identified in the first register transfer level code to the criteria defining a critical multiplex control structure;
(e) entering each of the multiplex control structures identified in the first register transfer level code that satisfy the criteria defining a critical multiplex control structure in a list of critical multiplex control structures; and
(f) generating as output the list of critical multiplex control structures.
9. The method of claim 8 further comprising a step of manually entering a multiplex control structure in the list of critical multiplex control structures.
10. The method of claim 8 further comprising a step of replacing each of the multiplex control structures in the list of critical multiplex control structures with corresponding non-critical multiplex control structures.
11. The method of claim 10 further comprising a step of generating as output a second register transfer level code for the integrated circuit design with the corresponding non-critical multiplex control structures.
12. The method of claim 8 further comprising including a variable and a threshold value for each variable in the criteria defining a critical multiplex control structure.
13. The method of claim 12 further comprising including a variable in the criteria defining a critical multiplex control structure for at least one of a number of buses, a number of signals per bus, a total number of signals, a number of register bank sources, a number of memory sources, a number of flip-flops, a number of start points, and a number of endpoints.
14. The method of claim 12 further comprising weighting the variable by a variable function of a priority value assigned to the variable.
15. A computer program product for optimizing register transfer level code for an integrated circuit design comprising a medium for embodying a computer program for input to a computer and a computer program embodied in the medium for causing the computer to perform steps of:
(a) receiving as input a first register transfer level code for the integrated circuit design;
(b) receiving as input criteria defining a critical multiplex structure;
(c) analyzing the first register transfer level code to identify all multiplex structures in the first register transfer level code;
(d) comparing each of the multiplex structures identified in the first register transfer level code to the criteria defining a critical multiplex structure;
(e) entering each of the multiplex structures identified in the first register transfer level code that satisfy the criteria defining a critical multiplex structure in a list of critical multiplex structures; and
(f) generating as output the list of critical multiplex structures.
16. The computer program product of claim 15 further comprising a step of manually entering a multiplex structure in the list of critical multiplex structures.
17. The computer program product of claim 15 further comprising a step of replacing each of the multiplex structures in the list of critical multiplex structures with corresponding non-critical multiplex structures.
18. The computer program product of claim 17 further comprising a step of generating as output a second register transfer level code for the integrated circuit design with the corresponding non-critical multiplex structures.
19. The computer program product of claim 15 further comprising including a variable and a threshold value for each variable in the criteria defining a critical multiplex structure.
20. The computer program product of claim 19 further comprising including a variable in the criteria defining a critical multiplex structure for at least one of a number of buses, a number of signals per bus, a total number of signals, a number of register bank sources, a number of memory sources, a number of flip-flops, a number of start points, and a number of endpoints.
21. The computer program product of claim 19 further comprising weighting the variable by a variable function of a priority value assigned to the variable.
22. A computer program product for optimizing register transfer level code for an integrated circuit design comprising a medium for embodying a computer program for input to a computer and a computer program embodied in the medium for causing the computer to perform steps of:
(a) receiving as input a first register transfer level code for the integrated circuit design;
(b) receiving as input criteria defining a critical multiplex control structure;
(c) analyzing the first register transfer level code to identify multiplex control structures in the first register transfer level code;
(d) comparing each of the multiplex control structures identified in the first register transfer level code to the criteria defining a critical multiplex control structure;
(e) entering each of the multiplex control structures identified in the first register transfer level code that satisfy the criteria defining a critical multiplex control structure in a list of critical multiplex control structures; and
(f) generating as output the list of critical multiplex control structures.
23. The computer program product of claim 22 further comprising a step of manually entering a multiplex control structure in the list of critical multiplex control structures.
24. The computer program product of claim 22 further comprising a step of replacing each of the multiplex control structures in the list of critical multiplex control structures with corresponding non-critical multiplex control structures.
25. The computer program product of claim 24 further comprising a step of generating as output a second register transfer level code for the integrated circuit design with the corresponding non-critical multiplex control structures.
26. The computer program product of claim 22 further comprising including a variable and a threshold value for each variable in the criteria defining a critical multiplex control structure.
27. The computer program product of claim 26 further comprising including a variable in the criteria defining a critical multiplex control structure for at least one of a number of buses, a number of signals per bus, a total number of signals, a number of register bank sources, a number of memory sources, a number of flip-flops, a number of start points, and a number of endpoints.
28. The computer program product of claim 26 further comprising weighting the variable by a variable function of a priority value.