Method and apparatus for DC offset cancellation in amplifiers
View Patent ↗A system, circuit, and method of canceling DC offset errors in cascaded amplifiers comprises arranging a plurality of any of analog voltage and analog current amplifier stages in any of cascaded and parallel configurations; operatively connecting a feedback comparator and digital logic in a feedback path around a given amplifier, wherein the digital logic comprises a finite state machine implementing an adaptive search algorithm comprising fixed switching and modulated switching; operatively connecting a switch at a differential input of the amplifier to short both input terminals of the amplifier; performing fixed switching on binary weighted elements generating discrete analog steps used to vary any of DC offset voltage and current at the input of the amplifier; and performing modulated switching on at least one lower least significant bit (LSB) of all bits used to vary the any of the DC offset voltage and current.
1. A method of canceling DC offset errors in cascaded amplifiers, said method comprising:
arranging a plurality of any of analog voltage and analog current amplifier stages in any of cascaded and parallel configurations;
operatively connecting a feedback comparator and digital logic in a feedback path around a given amplifier, wherein said digital logic comprises a finite state machine implementing an adaptive search algorithm comprising fixed switching and modulated switching;
operatively connecting a switch at a differential input of said amplifier to short both input terminals of said amplifier;
performing fixed switching on binary weighted elements generating discrete analog steps used to vary any of DC offset voltage and current at said input of said amplifier; and
performing modulated switching on at least one lower least significant bit (LSB) of all bits used to vary said any of said DC offset voltage and current.
2. The method of claim 1 , wherein said feedback comparator and said digital logic are configured around each said amplifier in a network of any of the cascaded and parallel amplifier stages.
3. The method of claim 1 , wherein said feedback comparator and said digital logic are shared for each said amplifier in a network of any of the cascaded and parallel amplifier stages, wherein a first stage in a chain of amplifiers is calibrated first, followed by a second stage amplifier, up to a Nth stage in a cascade of N amplifier stages.
4. The method of claim 1 , wherein the modulating process is performed by any of a carry out signal of an accumulator clocked with a high-speed clock and by an output signal of a digital sigma-delta modulator.
5. The method of claim 4 , wherein said digital sigma-delta modulator comprises any of a single-bit, multi-bit, MASH, single-loop, and any other digital sigma-delta modulator architecture.
6. The method of claim 1 , further comprising using only one switch for shorting the differential input terminals of a first amplifier in a cascade of amplifiers, wherein during DC offset error cancellation, said switch is closed and a DC offset error cancellation algorithm is run on each amplifier in series starting from said first amplifier in a chain of amplifiers proceeding to a last amplifier.
7. The method of claim 1 , wherein said adaptive search algorithm comprises any of a binary search algorithm and a linear search algorithm, wherein in said binary search algorithm, a most significant bit (MSB) is first asserted.
8. The method of claim 7 , wherein said adaptive search algorithm runs such that if an output voltage is less than a reference mode voltage, then said MSB is deasserted.
9. The method of claim 8 , wherein if said output voltage is greater than said reference mode voltage, then said MSB is asserted.
10. The method of claim 9 , wherein said binary search algorithm restarts with a second MSB and continues down to said LSB.
11. A circuit for canceling DC offset errors in cascaded amplifiers, said circuit comprising:
a plurality of any of analog voltage and analog circuit amplifier stages arranged in any of cascaded and parallel configurations;
a feedback path around a given amplifier, wherein said feedback path comprises a feedback comparator and digital logic, wherein said digital logic comprises a finite state machine implementing an adaptive search algorithm comprising fixed switching and modulated switching; and
a switch operatively connected at a differential input of said amplifier to short both input terminals of said amplifier,
wherein said fixed switching is performed on binary weighted elements generating discrete analog steps used to vary any of DC offset voltage and current at said input of said amplifier, and
wherein said modulated switching is performed on at least one lower least significant bit (LSB) of all bits used to vary said any of said DC offset voltage and current.
12. The circuit of claim 11 , wherein said feedback comparator and said digital logic are configured around each said amplifier in a network of any of the cascaded and parallel amplifier stages.
13. The circuit of claim 11 , wherein said feedback comparator and said digital logic are shared for each said amplifier in a network of any of the cascaded and parallel amplifier stages, wherein a first stage in a chain of amplifiers is calibrated first, followed by a second stage amplifier, up to a Nth stage in a cascade of N amplifier stages.
14. The circuit of claim 11 , wherein the modulating process is performed by any of a carry out signal of an accumulator clocked with a high-speed clock and by an output signal of a digital sigma-delta modulator.
15. The circuit of claim 14 , wherein said digital sigma-delta modulator comprises any of a single-bit, multi-bit, MASH, single-loop, and any other digital sigma-delta modulator architecture.
16. The circuit of claim 11 , wherein only one switch shorting the differential input terminals of a first amplifier in a cascade of amplifiers is used, and wherein during DC offset error cancellation, said switch is closed and a DC offset error cancellation algorithm is run on each amplifier in series starting from said first amplifier in a chain of amplifiers proceeding to a last amplifier.
17. The circuit of claim 11 , wherein said adaptive search algorithm comprises any of a binary search algorithm and a linear search algorithm, wherein in said binary search algorithm, a most significant bit (MSB) is first asserted.
18. The circuit of claim 17 , wherein said adaptive search algorithm runs such that if an output voltage is less than a reference mode voltage, then said MSB is deasserted.
19. The circuit of claim 18 , wherein if said output voltage is greater than said reference mode voltage, then said MSB is asserted.
20. The circuit of claim 19 , wherein said binary search algorithm restarts with a second MSB and continues down to said LSB.
21. A system for canceling DC offset errors in cascaded amplifiers, said system comprising:
a signal generator;
a plurality of any of analog voltage and analog circuit amplifiers stages arranged in any of cascaded and parallel configurations and adapted to receive signals from said signal generator;
a feedback path around a given amplifier, wherein said feedback path comprises a feedback comparator and digital logic, wherein said digital logic comprises a finite state machine implementing an adaptive search algorithm comprising fixed switching and modulated switching, wherein said feedback comparator and said digital logic are configured around each said amplifier in a network of any of the cascaded and parallel amplifier stages, wherein said feedback comparator and said digital logic are shared for each said amplifier in a network of any of the cascaded and parallel amplifier stages, wherein a first stage in a chain of amplifiers is calibrated first, followed by a second stage amplifier, up to a Nth stage in a cascade of N amplifier stages, wherein said adaptive search algorithm comprises any of a binary search algorithm and a linear search algorithm, wherein in said binary search algorithm, a most significant bit (MSB) is first asserted; and
a switch operatively connected at a differential input of said amplifier to short both input terminals of said amplifier,
wherein said fixed switching is performed on binary weighted elements generating discrete analog steps used to vary any of DC offset voltage and current at said input of said amplifier,
wherein said modulated switching is performed on at least one lower least significant bit (LSB) of all bits used to vary said any of said DC offset voltage and current, and wherein the modulating process is performed by any of a carry out signal of an accumulator clocked with a high-speed clock and by an output signal of a digital sigma-delta modulator.
22. The system of claim 21 , wherein said digital sigma-delta modulator comprises any of a single-bit, multi-bit, MASH, single-loop, and any other digital sigma-delta modulator architecture.
23. The system of claim 21 , wherein said adaptive search algorithm runs such that if an output voltage is less than a reference mode voltage, then said MSB is deasserted.
24. The system of claim 23 , wherein if said output voltage is greater than said reference mode voltage, then said MSB is asserted.
25. The system of claim 24 , wherein said binary search algorithm restarts with a second MSB and continues down to said LSB.