IP Library Granted Patent US 7,352,238
Granted Patent B2
US 7,352,238 · App. 11/472,138 · Granted Apr 1, 2008

dB-linear analog variable gain amplifier (VGA) realization system and method

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Quick Facts
Patent No.
US 7,352,238
App. No.
11/472,138
Granted
Apr 1, 2008
Kind
B2
Abstract

A dB-linear variable gain amplifier, a method for creation, and a system includes an amplifier; a pair of resistor arrays operatively connected to the amplifier, wherein each resistor array comprises MOS transistor resistive switches; a differential ramp-generator circuit operatively connected to the pair of resistor arrays; and voltage control lines generated by the differential ramp-generator circuit, wherein the voltage control lines are operatively connected to each of the MOS transistor resistive switches in the pair of resistor arrays. The number of the voltage control lines that are operatively connected to the each of the MOS transistor resistive switches is equal to the number of resistors in a particular resistor array. The differential ramp-generator circuit is preferably operable to take an automatic gain control voltage and generate a series of differential ramp voltages and apply the series of differential ramp voltages to one of the MOS transistor resistive switches.

Claims (34)

1. A method for creating a dB-linear variable gain amplifier (VGA), said method comprising:

operatively connecting a pair of resistor arrays to an operational amplifier, wherein each resistor array comprises metal oxide semiconductor (MOS) transistor switches;

operatively connecting a differential ramp-generator circuit to said pair of resistor arrays; and

said differential ramp-generator circuit comprising voltage control lines that apply voltage to a gate of each of said MOS transistor switches in said pair of resistor arrays.

2. The method of claim 1 , wherein the number of said voltage control lines that are used to apply voltage to said gate of each of said MOS transistor switches is equal to the number of resistors in a particular resistor array.

3. The method of claim 1 , further comprising said differential ramp-generator circuit taking an automatic gain control voltage, generating a series of differential ramp voltages, and applying said series of differential ramp voltages to one of said MOS transistor switches.

4. The method of claim 3 , wherein the conductance on a first of said pair of resistor arrays linearly and continuously increases while simultaneously the conductance on a second of said pair of resistor arrays linearly and continuously decreases as said automatic gain control voltage increases.

5. The method of claim 1 , further comprising operatively connecting a voltage source device in series with a virtual ground terminal of said operational amplifier.

6. The method of claim 1 , wherein said operational amplifier comprises a capacitance array operable to be gradually switched using said MOS transistor switches and ramp-generator signals generated by said differential ramp-generator circuit.

7. The method of claim 3 , further comprising operatively connecting an automatic gain control loop filter to differential ramp-generator circuit.

8. The method of claim 1 , further comprising said differential ramp-generator circuit taking an automatic gain control voltage, generating a series of differential ramp voltages, and applying said series of differential ramp voltages to multiple operational amplifiers.

9. A variable gain amplifier (VGA) comprising:

an amplifier;

a pair of resistor arrays operatively connected to said amplifier, wherein each resistor array comprises metal oxide semiconductor (MOS) transistor resistive switches;

a differential ramp-generator circuit operatively connected to said pair of resistor arrays; and

voltage control lines generated by said differential ramp-generator circuit, wherein said voltage control lines are operatively connected to each of said MOS transistor resistive switches in said pair of resistor arrays.

10. The VGA of claim 9 , wherein the number of said voltage control lines that are operatively connected to said each of said MOS transistor resistive switches is equal to the number of resistors in a particular resistor array.

11. The VGA of claim 9 , wherein said differential ramp-generator circuit is operable to take an automatic gain control voltage and generate a series of differential ramp voltages and apply said series of differential ramp voltages to one of said MOS transistor resistive switches.

12. The VGA of claim 11 , wherein the conductance on a first of said pair of resistor arrays linearly and continuously increases while simultaneously the conductance on a second of said pair of resistor arrays linearly and continuously decreases as said automatic gain control voltage increases.

13. The VGA of claim 9 , further comprising a voltage source device operatively connected in series with a virtual ground terminal of said amplifier.

14. The VGA of claim 9 , wherein said amplifier comprises a capacitance away operable to be gradually switched using said MOS transistor resistive switches and ramp-generator signals generated by said differential ramp-generator circuit.

15. The VGA of claim 11 , further comprising an automatic gain control loop filter operatively connected to said differential ramp-generator circuit.

16. The VGA of claim 9 , wherein said differential ramp-generator circuit is operable to take an automatic gain control voltage and generate a series of differential ramp voltages and apply said series of differential ramp voltages to multiple operational amplifiers.

17. A system comprising:

an operational amplifier;

at least one set of resistor arrays operatively connected to said operational amplifier, wherein each resistor array comprises metal oxide semiconductor (MOS) transistor switches; and

a differential ramp-generator circuit operatively connected to said at least one set of resistor arrays, wherein said differential ramp-generator circuit is operable to generate voltage control lines that apply voltage to a gate of each of said MOS transistor switches in said at least one set of resistor arrays.

18. The system of claim 17 , wherein the number of said voltage control lines that are used to apply voltage to said gate of each of said MOS transistor switches is equal to the number of resistors in a particular resistor array.

19. The system of claim 17 , wherein said differential ramp-generator circuit is operable to take an automatic gain control voltage and generate a series of differential ramp voltages and apply said series of differential ramp voltages to one of said MOS transistor switches.

20. The system of claim 19 , wherein the conductance on a first of said at least one set of resistor arrays linearly and continuously increases while simultaneously the conductance on a second of said at least one set of resistor arrays linearly and continuously decreases as said automatic gain control voltage increases.

21. The system of claim 17 , further comprising a voltage source device operatively connected in series with a virtual ground terminal of said operational amplifier.

22. The system of claim 17 , wherein said operational amplifier comprises a capacitance array operable to be gradually switched using said MOS transistor switches and ramp-generator signals generated by said differential ramp-generator circuit.

23. The system of claim 19 , further comprising an automatic gain control loop filter operatively connected to said differential ramp-generator circuit.

24. The system of claim 17 , wherein said differential ramp-generator circuit is operable to take an automatic gain control voltage and generate a series of differential ramp voltages and apply said series of differential ramp voltages to multiple operational amplifiers.

Assignments (31)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Apr 6, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: ATMEL WIRELESS MCU TECHNOLOGIES CORPORATION
Reel/Frame 038364/0615 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Apr 6, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: NEWPORT MEDIA, INC.
Reel/Frame 038364/0659 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 24, 2014
From: NEWPORT MEDIA, INC.
To: ATMEL CORPORATION
Reel/Frame 034705/0090 →
TERMINATION OF SECURITY Recorded Oct 7, 2014
From: BRIDGE BANK, NATIONAL ASSOCIATION
To: ATMEL CORPORATION
Reel/Frame 033907/0517 →
TERMINATION OF SECURITY Recorded Oct 7, 2014
From: PINNACLE VENTURES, L.L.C.
To: ATMEL CORPORATION
Reel/Frame 033908/0435 →
TERMINATION OF SECURITY Recorded Oct 7, 2014
From: PINNACLE VENTURES, L.L.C.
To: ATMEL CORPORATION
Reel/Frame 033908/0379 →
TERMINATION OF SECURITY Recorded Oct 7, 2014
From: NEWPORT MEDIA, INC.
To: ATMEL CORPORATION
Reel/Frame 033908/0242 →
TERMINATION OF SECURITY Recorded Oct 7, 2014
From: NEWPORT MEDIA, INC.
To: ATMEL CORPORATION
Reel/Frame 033907/0775 →
TERMINATION OF SECURITY Recorded Oct 7, 2014
From: NEWPORT MEDIA, INC.
To: ATMEL CORPORATION
Reel/Frame 033907/0748 →
TERMINATION OF SECURITY Recorded Oct 7, 2014
From: HORIZON TECHNOLOGY FINANCE CORPORATION
To: ATMEL CORPORATION
Reel/Frame 033907/0702 →
PATENT SECURITY AGREEMENT Recorded Sep 5, 2014
From: NEWPORT MEDIA, INC.
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 033689/0195 →
PATENT SECURITY AGREEMENT Recorded Sep 5, 2014
From: ATMEL WIRELESS MCU TECHNOLOGIES CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC., AS COLLATERAL AGENT
Reel/Frame 033689/0214 →
SECURITY AGREEMENT Recorded Mar 1, 2013
From: NEWPORT MEDIA, INC.
To: HORIZON TECHNOLOGY FINANCE CORPORATION, AS COLLATERAL AGENT
Reel/Frame 029956/0891 →
SECURITY AGREEMENT Recorded Feb 15, 2013
From: NEWPORT MEDIA, INC., A DELAWARE CORPORATION; NEWPORT MEDIA, INC., A CALIFORNIA CORPORATION
To: PINNACLE VENTURES, L.L.C.
Reel/Frame 029818/0138 →
SECURITY AGREEMENT Recorded Dec 31, 2012
From: NEWPORT MEDIA, INC.
To: BRIDGE BANK, NATIONAL ASSOCIATION
Reel/Frame 029554/0118 →
SECURITY AGREEMENT Recorded May 31, 2012
From: NEWPORT MEDIA, INC.
To: PINNACLE VENTURES, L.L.C.
Reel/Frame 028299/0903 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Jun 21, 2006
From: ELWAN, HASSAN; FAHIM, AMR; ISMAIL, ALY; YOUSSOUFIAN, EDWARD
To: NEWPORT MEDIA, INC.
Reel/Frame 018027/0764 →