Multiple-transistor structure systems and methods in which portions of a first transistor and a second transistor are formed from the same layer
View Patent ↗A semiconductor structure is fabricated with two different portions. The first portion forms a first transistor, while the second portion forms a second transistor. Notably, portions of the first transistor also a make up portions of the second transistor. That is, both the first transistor and the second transistor are made of portions of the same structure.
1. A transistor structure, comprising:
a first lateral transistor having a base portion and an emitter portion; and
a second vertical transistor having a base and a collector;
wherein a first epitaxial region:
serves both as the emitter portion of the first transistor and as the base of the second transistor, and
forms a heterojunction with an emitter of the second transistor; and
wherein a second epitaxial region serves both as the base portion of the first transistor and as the collector of the second transistor: and
wherein the base portion of the first transistor further comprises an n + semiconductor layer and an n − semiconductor layer.
2. The transistor structure of claim 1 wherein the n + semiconductor layer and the n − semiconductor layer are GaAs layers.
3. The transistor structure of claim 1 , wherein the first epitaxial region comprises a p + semiconductor layer.
4. The transistor structure of claim 3 , wherein the p + semiconductor layer is a GaAs layer.
5. The transistor structure of claim 1 , wherein a collector portion of the first transistor is placed at a distance from the emitter portion of the first transistor so that the first transistor has a DC current gain of at least 0.1.
6. The transistor structure of claim 1 wherein the emitter portion of the first transistor is electrically connected to a voltage source and the collector portion of the first transistor is electrically connected to a power amplifier circuit, so that the first transistor is configured as a switch between the voltage source and the power amplifier circuit.
7. The transistor structure of claim 6 wherein the switch has a shutdown current having a magnitude of less than approximately 1 μA.
8. The transistor structure of claim 6 , wherein a collector portion of the first transistor is placed at a distance from the emitter portion of the first transistor so that the first transistor has a DC current gain of at least 0.1.
9. The transistor structure of claim 1 , wherein the first epitaxial region further serves as a collector portion of the first transistor.
10. A transistor structure, comprising:
a first lateral transistor having a base portion and an emitter portion; and
a second vertical transistor having a base and a collector:
wherein a first epitaxial region:
serves both as the emitter portion of the first transistor and as the base of the second transistor, and
forms a heterojunction with an emitter of the second transistor; and
wherein a second epitaxial region serves both as the base portion of the first transistor and as the collector of the second transistor; and
wherein the emitter of the second transistor further comprises an n − semiconductor layer and an n + semiconductor layer.
11. The transistor structure of claim 10 wherein the emitter portion of the first transistor is electrically isolated from the base of the second transistor, and wherein the base portion of the first transistor is electrically isolated from the collector of the second transistor.
12. The transistor structure of claim 10 wherein the base portion of the first transistor further comprises an n + semiconductor layer and an n − semiconductor layer.
13. The transistor structure of claim 10 , wherein the emitter portion of the first transistor further comprises a p + semiconductor layer.
14. The transistor structure of claim 10 , wherein a collector portion of the first transistor is placed at a distance from the emitter portion of the first transistor so that the first transistor has a DC current gain of at least 0.1.
15. A semiconductor device, comprising:
a first n + semiconductor layer;
a second n − semiconductor layer fabricated upon the first n + semiconductor layer, with the second n − semiconductor layer etched to form both a base portion of a lateral transistor and a collector of a vertical transistor; and
a third p + semiconductor layer fabricated upon the second n − semiconductor layer, and having a first portion placed at a distance from a second portion, with the third p + semiconductor layer etched to form both an emitter portion of the lateral transistor and a base of the vertical transistor;
wherein the base of the vertical transistor forms a heterojunction with an emitter of the second vertical transistor.
16. The semiconductor device of claim 15 , wherein:
the first n + semiconductor layer and the second n − semiconductor layer are configured as a base of a first transistor and as a collector of a second transistor;
the first portion of the third p + semiconductor layer is configured as a collector of the first transistor; and
the second portion of the third p + semiconductor layer is configured as an emitter of the first transistor.
17. The semiconductor device of claim 16 wherein the first transistor is a homojunction bipolar junction transistor, and the second transistor is a heterogeneous bipolar junction transistor.
18. The semiconductor device of claim 16 wherein the distance has a magnitude corresponding to a DC current gain of the first transistor, and wherein the DC current gain is at least 0.1.
19. The semiconductor device of claim 16 further comprising a switch circuit including the first transistor, the switch circuit configured to control a voltage between a voltage source and a power amplifier circuit according to a shutdown current, wherein:
the first portion is electrically connected to the power amplifier circuit;
the second portion is electrically connected to the voltage source, so that the first transistor is configured as a switch between the voltage source and the power amplifier circuit; and
the magnitude of the shutdown current is less than approximately 1 μA.
20. The semiconductor device of claim 16 , further comprising:
a fourth N − semiconductor layer fabricated upon the third p + semiconductor layer; and
a fifth n + semiconductor layer fabricated upon the fourth n − semiconductor layer.
21. The semiconductor device of claim 18 , wherein:
at least one of the first portion and the second portion is configured as a base of the first transistor; and
the fourth N − semiconductor layer and the fifth n + semiconductor layer are configured as an emitter of the second transistor.
22. The semiconductor device of claim 16 wherein:
the first n + semiconductor layer has a first portion and a second portion electrically isolated from the first portion;
the second n − semiconductor layer has a first portion and a second portion electrically isolated from the first portion;
the third p + semiconductor layer has a third portion electrically isolated from its first portion and its second portion;
the first portion of the first n + semiconductor layer and the first portion of the second n − semiconductor layer are configured as the base of the first transistor;
the second portion of the first n + semiconductor layer and the second portion of the second n − semiconductor layer are configured as the collector of the second transistor; and
the third portion of the third p + semiconductor layer is configured as a base of the second transistor.
23. The semiconductor device of claim 15 wherein the first n + semiconductor layer, the second n + semiconductor layer, and the third p + semiconductor layer are GaAs layers.
24. A switch circuit, comprising:
a first terminal configured for electrical connection to a voltage source;
a second terminal configured for electrical connection to a rower amplifier;
a first lateral switch transistor configured to control an application of a voltage from the voltage source to the power amplifier according to a switch signal; and
a second vertical switch transistor configured to control an application of the switch signal to the first switch transistor according to a shutdown current:
wherein at least one n-doped semiconductor layer comprises a base of the first switch transistor and a collector of the second transistor:
wherein a p-doped semiconductor layer comprises a collector and an emitter of the first switch transistor, and a base of the second switch transistor; and
wherein the base of the second switch transistor forms a heterojunction with an emitter of the second switch transistor:
wherein the at least one n-doped semiconductor layer further comprises a first semiconductor layer that is an n + semiconductor layer, and a second semiconductor layer that is an n − semiconductor layer.
25. The switch circuit of claim 24 , wherein
the first switch transistor has an emitter terminal connected to the first terminal, a collector terminal connected to the second terminal, and a base terminal; and
the second switch transistor has a collector terminal in electrical communication with the first terminal through a resistor and in electrical communication with the base terminal of the first switch transistor, a grounded emitter terminal, and a base terminal configured to receive the shutdown current.
26. The switch circuit of claim 24 wherein the n + semiconductor layer and the n − semiconductor layer are GaAs layers.
27. The switch circuit of claim 24 wherein the p-doped semiconductor layer is a p + semiconductor layer.
28. The switch circuit of claim 27 wherein the p + semiconductor layer is a GaAs layer.
29. The switch circuit of claim 24 wherein the first switch transistor is a bipolar junction transistor.