IP Library Granted Patent US 7,271,485
Granted Patent B1
US 7,271,485 · App. 11/530,550 · Granted Sep 18, 2007

Systems and methods for distributing I/O in a semiconductor device

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Quick Facts
Patent No.
US 7,271,485
App. No.
11/530,550
Granted
Sep 18, 2007
Kind
B1
Abstract

Various systems and methods for implementing multi-mode semiconductor devices are discussed herein. For example, a multi-mode semiconductor device is disclosed that includes a device package with a number of package pins. In addition, the device includes a semiconductor die with at least two IO buffers. One of the IO buffers is located a distance from a particular package pin and another of the IO buffers is located a greater distance from the particular package pin. The IO buffer located closest to the package pin includes first bond pad electrically coupled to a circuit implementing a first interface type and a first floating bond pad, and the other IO buffer includes a second bond pad electrically coupled to a circuit implementing a second interface type and a second floating bond pad. In some cases, the first floating bond pad is electrically coupled to the circuit implementing the second interface type via a metal layer wire, and the first floating bond pad is electrically coupled to the particular package pin.

Claims (45)

1. A multi-mode semiconductor device, wherein the semiconductor device comprises:

a device package, wherein the device package includes a package pin; and

a semiconductor die, wherein the semiconductor die includes:

a first IO buffer located a first distance from the package pin and a second IO buffer located a second distance from the package pin, wherein the first distance is less than the second distance, wherein the first IO buffer includes a first bond pad electrically coupled to a circuit implementing a first interface type and a floating bond pad, and wherein the second IO buffer includes a second bond pad electrically coupled to a circuit implementing a second interface type.

2. The semiconductor device of claim 1 , wherein the floating bond pad is electrically coupled to the circuit implementing the second interface type via a metal layer wire, and wherein the floating bond pad is electrically coupled to the package pin.

3. The semiconductor device of claim 2 , wherein the metal layer wire is on a metal layer at a level coincident with the first floating bond pad.

4. The semiconductor device of claim 3 , wherein the metal layer is an aluminum metal layer, and wherein the floating bond pad is formed of aluminum.

5. The semiconductor device of claim 2 , wherein the second interface type is selected from a group consisting of:

a USB interface,

a 1394 interface, and

an ATA interface.

6. The semiconductor device of claim 1 , wherein:

the first bond pad is electrically coupled to the circuit implementing the first interface type by way of a first via extending substantially vertically below the first bond pad; and

the second bond pad is electrically coupled to the circuit implementing the second interface type by way of a second via extending substantially vertically below the second bond pad.

7. The semiconductor device of claim 6 , wherein the second bond pad is implemented in aluminum, and wherein the via connects the second bond pad to a copper metal layer.

8. A multiple IO supporting semiconductor device, the semiconductor device comprising:

an IO buffer, wherein the IO buffer is located in proximity to a device package pin, wherein the IO buffer includes a first bond pad and a second bond pad, and wherein only one of the first bond pad and the second bond pad is electrically coupled to the device package pin;

wherein the first bond pad is electrically coupled to a driver circuit element via a metal layer wire on a metal layer at a level coincident with the first bond pad; and

wherein the metal layer is an aluminum metal layer.

9. The semiconductor device of claim 8 , wherein one of the first bond pad and the second bond pad is a floating pad.

10. The semiconductor device of claim 8 , wherein the driver circuit element is a first driver circuit element, wherein the second bond pad is electrically coupled to a second driver circuit element by way of a via extending substantially vertically below the second bond pad.

11. The semiconductor device of claim 10 , wherein the second bond pad is implemented in aluminum, and wherein the via connects the second bond pad to a copper metal layer.

12. The semiconductor die of claim 11 , wherein at least one of the first bond pad and the second bond pad is implemented using CUP technology.

13. The semiconductor device of claim 10 , wherein the first driver circuit element is associated with a first interface type, and wherein the second driver circuit element is associated with a second interface type.

14. The semiconductor device of claim 10 , wherein:

the device package pin is associated with a device package;

wherein the device package encapsulates the semiconductor device; and

wherein only one of the first interface type and the second interface type is provided at the IO of the device package.

15. The semiconductor device of claim 14 , wherein the both the first interface type and the second interface type are available on the semiconductor device.

16. A method for manufacturing a multi-mode semiconductor device, the methods comprise:

providing a semiconductor die, wherein the semiconductor die includes a first IO buffer and a second IO buffer, wherein the first IO buffer includes a first bond pad electrically coupled to a circuit implementing a first interface type and a floating bond pad, and wherein the second IO buffer includes a second bond pad electrically coupled to a circuit implementing a second interface type;

providing a package, wherein the package includes a package pin;

forming a metallization layer;

forming a wire in the metallization layer, wherein the floating bond pad is electrically coupled to the second bond pad, wherein the floating bond pad is electrically coupled to the circuit implementing the second interface type via the second bond pad; and

placing a bond wire electrically coupling the floating bond pad to the package pin.

17. The method of claim 16 , wherein the metallization layer is on the same level as the floating bond pad.

18. The method of claim 16 , wherein:

the first interface type is selected from a group consisting of:

a USB interface,

a 1394 interface, and

an ATA interface; and

the second interface type is selected from a group consisting of:

a USB interface,

a 1394 interface, and

an ATA interface.

Assignments (12)
RELEASE OF SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 059723/0382 →
SECURITY INTEREST Recorded Apr 15, 2022
From: CORTLAND CAPITAL MARKET SERVICES LLC
To: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
Reel/Frame 060885/0001 →
SECURITY INTEREST Recorded Feb 1, 2018
From: HILCO PATENT ACQUISITION 56, LLC; BELL SEMICONDUCTOR, LLC; BELL NORTHERN RESEARCH, LLC
To: CORTLAND CAPITAL MARKET SERVICES LLC, AS COLLATERAL AGENT
Reel/Frame 045216/0020 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0001 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 17, 2017
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.; BROADCOM CORPORATION
To: BELL SEMICONDUCTOR, LLC
Reel/Frame 044886/0766 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENTS Recorded Feb 3, 2017
From: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 041710/0001 →
PATENT SECURITY AGREEMENT Recorded Feb 11, 2016
From: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
To: BANK OF AMERICA, N.A., AS COLLATERAL AGENT
Reel/Frame 037808/0001 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT RIGHTS (RELEASES RF 032856-0031) Recorded Feb 2, 2016
From: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
To: LSI CORPORATION; AGERE SYSTEMS LLC
Reel/Frame 037684/0039 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Feb 20, 2015
From: AGERE SYSTEMS LLC
To: AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
Reel/Frame 035059/0001 →
MERGER Recorded Feb 20, 2015
From: AGERE SYSTEMS INC.
To: AGERE SYSTEMS LLC
Reel/Frame 035058/0895 →
PATENT SECURITY AGREEMENT Recorded May 8, 2014
From: LSI CORPORATION; AGERE SYSTEMS LLC
To: DEUTSCHE BANK AG NEW YORK BRANCH, AS COLLATERAL AGENT
Reel/Frame 032856/0031 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Sep 11, 2006
From: MADHANI, PARAG; BARNES, PAUL F; HAWK, JR., DONALD E; PRABAKARAN, KANDASWAMY
To: AGERE SYSTEMS INC.
Reel/Frame 018229/0590 →