High speed logic level shifter
View Patent ↗A circuit for transmitting logic signals across a high voltage barrier has a logic signal buffer with true and complement state differential outputs. A binary flip-flop with set and reset inputs is further provided. A first coupling capacitor is coupled to the true buffer output and to the set input of the binary flip-flop. A second coupling capacitor is coupled to the complement buffer output and to the reset input of the binary flip-flop circuit.
1. A circuit for transmitting logic signals across a high voltage barrier comprising:
a logic signal buffer with true and complement state differential outputs;
a binary flip-flop with set and reset inputs;
a first coupling capacitor coupled to the true buffer output and to the set input of the binary flip-flop;
a second coupling capacitor coupled to the complement buffer output and to the reset input of the binary flip-flop circuit;
a reset signal circuit coupled to the logic signal buffer for setting the circuit to a known initial state; and
a logic gate for preventing a flow of input signal information during times a reset signal is active.
2. A circuit for transmitting logic signals across a high voltage barrier in accordance with claim 1 further comprising an output signal buffer coupled to the binary flip-flop.
3. A circuit for transmitting logic signals across a high voltage barrier in accordance with claim 1 wherein the logic signal buffer is constructed using CMOS technology.
4. A circuit for transmitting logic signals across a high voltage barrier in accordance with claim 1 wherein the binary flip-flop is constructed using CMOS technology.
5. A circuit for transmitting logic signals across a high voltage barrier in accordance with claim 1 wherein the first coupling capacitor and the second coupling capacitor each have a lower plate having an excess substrate capacitance coupled to the logic signal buffer to minimize parasitic capacitance.
6. A circuit for transmitting logic signals across a high voltage barrier in accordance with claim 1 further comprising a DC coupled level translator for coupling the reset signal circuit to the binary flip-flop circuit.
7. A circuit for transmitting logic signals across a high voltage barrier in accordance with claim 1 further comprising a delay circuit coupled to the reset signal circuit and to the logic gate.
8. A circuit for transmitting logic signals across a high voltage barrier comprising:
a logic signal buffer with true and complement state differential outputs;
a binary flip-flop with set and reset inputs,
a first coupling capacitor coupled to the true buffer output and to the set input of the binary flip-flop;
a second coupling capacitor coupled to the complement buffer output and to the reset input of the binary flip-flop circuit;
a reset signal circuit coupled to the logic signal buffer for setting the circuit to a known initial state; and
a power supply under voltage detection circuit to provide said reset signal.
9. A circuit for transmitting logic signals across a high voltage barrier comprising:
a logic signal buffer with true and complement state differential outputs;
a binary flip-flop with set and reset inputs;
a first coupling capacitor coupled to the true buffer output and to the set input of the binary flip-flop;
a second coupling capacitor coupled to the complement buffer output and to the reset input of the binary flip-flop circuit; and
means for detecting a rate of change of at least one circuit power supplies, and providing a reset signal whenever a power supply voltage rate of change exceeds a chosen value.
10. A circuit for transmitting logic signals across a high voltage barrier comprising:
a logic signal buffer with true and complement state differential outputs;
a binary flip-flop with set and reset inputs;
a first coupling capacitor coupled to the true buffer output and to the set input of the binary flip-flop;
a second coupling capacitor coupled to the complement buffer output and to the reset input of the binary flip-flop circuit; and
a logic comparison circuit having a first input coupled to the logic signal buffer and a second input coupled to the binary flip- flop output.
11. A circuit for transmitting logic signals across a high voltage barrier in accordance with claim 10 wherein an output of the logic comparison circuit is coupled to at least one of the set or reset inputs of the flip-flop.
12. A circuit for transmitting logic signals across a high voltage barrier in accordance with claim 8 further comprising an output signal buffer coupled to the binary flip-flop.
13. A circuit for transmitting logic signals across a high voltage barrier in accordance with claim 8 wherein the first coupling capacitor and the second coupling capacitor each have a lower plate having an excess substrate capacitance coupled to the logic signal buffer to minimize parasitic capacitance.
14. A circuit for transmitting logic signals across a high voltage barrier in accordance with claim 8 further comprising a DC coupled level translator for coupling the reset signal circuit to the binary flip-flop circuit.
15. A circuit for transmitting logic signals across a high voltage barrier in accordance with claim 8 further comprising a delay circuit coupled to the reset signal circuit and to the logic gate.
16. A circuit for transmitting logic signals across a high voltage barrier in accordance with claim 8 further comprising an output signal buffer coupled to the binary flip-flop.
17. A circuit for transmitting logic signals across a high voltage barrier in accordance with claim 9 wherein the first coupling capacitor and the second coupling capacitor each have a lower plate having an excess substrate capacitance coupled to the logic signal buffer to minimize parasitic capacitance.
18. A circuit for transmitting logic signals across a high voltage barrier in accordance with claim 9 further comprising a DC coupled level translator for coupling the reset signal circuit to the binary flip-flop circuit.
19. A circuit for transmitting logic signals across a high voltage barrier in accordance with claim 9 further comprising a delay circuit coupled to the reset signal circuit and to the logic gate.