Multi-level routing architecture in a field programmable gate array having transmitters and receivers
View Patent ↗A routing architecture in a field programmable gate array (FPGA) having a plurality of logic clusters wherein each logic cluster has at least two sub-clusters. The logic clusters are arranged in rows and columns and each logic clusters has a plurality of receiver components, a plurality of transmitter components, at least one buffer module, at least one sequential logic component and at least one combinatorial logic component. A first-level routing architecture is programmably coupled to the logic clusters and a second-level routing architecture is programmably coupled to the logic clusters and to the first-level routing architecture through at least one of the transmitter components and at least one of the receiver components.
1. A field programmable gate array (FPGA) comprising:
a plurality of logic clusters arranged in rows and columns, each logic cluster comprising:
a plurality of receiver modules,
a plurality of transmitter modules,
at least one buffer module,
at least one sequential logic component, and
a first combinatorial logic component;
a first-level routing architecture programmably coupled to said logic clusters; and
a second-level routing architecture programmably coupled to the first-level routing architecture through at least one of said transmitter modules and at least one of said receiver modules,
wherein at least one of said plurality of transmitter modules can transmit signals from said first-level routing architecture to said second-level routing architecture and can transmit signals from a vertical channel of said second-level routing architecture to a plurality of horizontal channels of said second-level routing architecture.
2. The FPGA of claim 1 , wherein at least one of said plurality of transmitter modules comprises:
an AND gate having three inputs and an output, wherein at least one of said inputs is coupled to said first-level routing architecture and one of said inputs is coupled to said second-level routing architecture; and
a buffer module having an input coupled to said output of said AND gate and an output coupled to said second-level routing architecture.
3. The FPGA of claim 2 , wherein at least one of said plurality of receiver modules comprises:
a buffer having an input coupled to said second-level routing architecture and an output coupled to an output track in said first-level routing architecture, wherein at least one of said plurality of receiver modules can receive signals from said second-level routing architecture and transmit said signals to said first-level routing architecture.
4. The FPGA of claim 2 , wherein said transmitter modules are coupled to every other second-level vertical channel within the same logic cluster column.
5. The FPGA of claim 1 , wherein said first-level routing architecture and said second-level routing architecture each comprises vertical channels and horizontal channels programmably coupled to said logic clusters.
6. The FPGA of claim 5 , wherein:
any horizontal channel in said second-level routing architecture has access to any vertical channel in said second-level routing architecture; and
any vertical channel in said second-level routing architecture has access to any horizontal channel in said second-level routing architecture.
7. The FPGA of claim 1 , further comprising:
a plurality of input/output clusters, each input/output cluster comprising:
an input/output module;
a plurality of receiver modules;
a transmitter module; and
a buffer module.
8. A method of providing a field programmable gate array (FPGA) comprising:
providing a plurality of logic clusters arranged in rows and columns, each logic cluster comprising:
a plurality of receiver modules,
a plurality of transmitter modules,
at least one buffer module,
at least one sequential logic component, and
a first combinatorial logic component;
providing a first-level routing architecture programmably coupled to said logic clusters; and
providing a second-level routing architecture programmably coupled to the first-level routing architecture through at least one of said transmitter modules and at least one of said receiver modules,
wherein at least one of said plurality of transmitter modules can transmit signals from said first-level routing architecture to said second-level routing architecture and can transmit signals from a vertical channel of said second-level routing architecture to a plurality of horizontal channels of said second-level routing architecture.
9. The method of claim 8 , wherein at least one of said plurality of transmitter modules comprises:
an AND gate having three inputs and an output, wherein at least one of said inputs is coupled to said first-level routing architecture and one of said inputs is coupled to said second-level routing architecture; and
a buffer module having an input coupled to said output of said AND gate and an output coupled to said second-level routing architecture.
10. The method of claim 9 , wherein at least one of said plurality of receiver modules comprises:
a buffer having an input coupled to said second-level routing architecture and an output coupled to an output track in said first-level routing architecture, wherein at least one of said plurality of receiver modules can receive signals from said second-level routing architecture and transmit said signals to said first-level routing architecture.
11. The method of claim 9 , wherein said transmitter modules are coupled to every other second-level vertical channel within the same logic cluster column.
12. The method of claim 8 , wherein said first-level routing architecture and said second-level routing architecture each comprises vertical channels and horizontal channels programmably coupled to said logic clusters.
13. The method of claim 12 , wherein:
any horizontal channel in said second-level routing architecture has access to any vertical channel in said second-level routing architecture; and
any vertical channel in said second-level routing architecture has access to any horizontal channel in said second-level routing architecture.
14. The method of claim 8 , further comprising:
providing a plurality of input/output clusters, each input/output cluster comprising:
an input/output module;
a plurality of receiver modules;
a transmitter module; and
a buffer module.