Field effect transistor with raised source/drain fin straps
View Patent ↗Therefore, disclosed above are embodiments of a multi-fin field effect transistor structure (e.g., a multi-fin dual-gate FET or tri-gate FET) that provides low resistance strapping of the source/drain regions of the fins, while also maintaining low capacitance to the gate by raising the level of the straps above the level of the gate. Embodiments of the structure of the invention incorporate either conductive vias or taller source/drain regions in order to electrically connect the source/drain straps to the source/drain regions of each fin. Also, disclosed are embodiments of associated methods of forming these structures.
1. A field effect transistor comprising:
an isolation layer;
a plurality of semiconductor fins on said isolation layer, wherein said semiconductor fins are parallel and wherein each of said semiconductor fins has end portions, has a center portion between said end portions and comprises source/drain regions within said end portions and a channel region within said center portion between said source/drain regions;
a gate covering said channel region of each of said fins; and
a conductor that traverses and is electrically connected to each of said fins at an end, wherein a first distance between said isolation layer and a top surface of said gate is less than a second distance between said isolation layer and a bottom surface of said conductor.
2. The field effect transistor of claim 1 , wherein said conductor comprises a metal strap.
3. The field effect transistor of claim 1 , wherein said conductor comprises one of a copper strap and a tungsten strap.
4. The field effect transistor of claim 1 , further comprising a second conductor that traverses and is electrically connected to each of said fins at second end.
5. The field effect transistor of claim 1 , wherein said source/drain regions are wider than said channel region in each of said fins.
6. A field effect transistor comprising:
an isolation layer;
a plurality of semiconductor fins on said isolation layer, wherein said semiconductor fins are parallel and wherein each of said semiconductor fins has end portions, has a center portion between said end portions and comprises source/drain regions within said end portions and a channel region within said center portion between said source/drain regions;
a gate covering said channel region of each of said fins;
a conductor that traverses each said fins at an end; and
a plurality of vias that electrically connect said fins at said end to said conductor, wherein a first distance between said isolation layer and a top surface of said gate is less than a second distance between said isolation layer and a bottom surface of said conductor.
7. The field effect transistor of claim 6 , wherein said conductor comprises a metal strap.
8. The field effect transistor of claim 6 , wherein said conductor comprises a copper strap and wherein said vias comprise copper-filled vias.
9. The field effect transistor of claim 6 , further comprising a conductive liner in said vias, wherein said conductive liner comprises one of titanium, titanium nitride, tantalum and tantalum nitride.
10. The field effect transistor of claim 6 , wherein a predetermined length of said vias is greater than a height of said gate above said fins.
11. The field effect transistor of claim 6 , further comprising a second conductor that traverses and is electrically connected to each of said fins at a second end.
12. The field effect transistor of claim 6 , wherein said source/drain regions are wider than said channel region in each of said fins.
13. A field effect transistor comprising:
an isolation layer;
a plurality of semiconductor fins on said isolation layer, wherein said semiconductor fins are parallel and wherein each of said semiconductor fins has end portions, has a center portion between said end portions and comprises source/drain regions within said end portions and a channel region within said center portion between said source/drain regions;
a gate covering said channel region of each of said fins; and
a conductor that traverses and is electrically connected to each of said fins at an end,
wherein said channel region has a first height that is shorter than a second height of said source/drain regions such that a first distance between said isolation layer and a top surface of said gate is less than a second distance between said isolation layer and a bottom surface of said conductor.
14. The field effect transistor of claim 13 , wherein said conductor comprises a metal strap.
15. The field effect transistor of claim 13 , wherein said conductor comprises a tungsten strap.
16. The field effect transistor of claim 13 , wherein said second height is approximately twice said first height.
17. The field effect transistor of claim 13 , wherein a top portion of each of said fins in said source/drain regions comprises a silicide.
18. The field effect transistor of claim 13 , wherein a top half of each of said fins in said source/drain regions comprises a silicide.
19. The field effect transistor of claim 13 , further comprising a second conductor that traverses and is electrically connected to each of said fins at a second end.
20. The field effect transistor of claim 13 , wherein said source/drain regions are wider than said channel region in each of said fins.