IP Library Granted Patent US 7,659,756
Granted Patent B2
US 7,659,756 · App. 11/535,152 · Granted Feb 9, 2010

MOSFET transistor amplifier with controlled output current

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Quick Facts
Patent No.
US 7,659,756
App. No.
11/535,152
Granted
Feb 9, 2010
Kind
B2
Abstract

A switched current source has a first voltage source, a second voltage source, and a third voltage source. A first transistor has a drain terminal coupled to one terminal of a load and a source terminal coupled to the third voltage source. A second transistor has drain, gate and source terminals. The drain terminal of the second transistor is coupled to the gate terminal of the first transistor. The source terminal of the second transistor is coupled to the source terminal of the first transistor. The gate terminal of the second transistor is coupled to the first voltage source. A third transistor has drain, gate and source terminals. The drain terminal of the third transistor is coupled to the gate terminal of the first transistor. The source terminal of the third transistor is coupled to the second voltage source. The gate terminal of the third transistor is coupled to the first voltage source.

Claims (60)

1. A switched current source comprising:

a first voltage source, wherein the first voltage source is an independent controlled voltage source;

a second voltage source;

a third voltage source;

a first transistor having a drain terminal connected to one terminal of a load and a source terminal connected to the first voltage source, the second voltage source, and the third voltage source;

a second transistor having drain, gate and source terminals wherein the drain terminal of the second transistor is connected to the gate terminal of the first transistor, the source terminal of the second transistor is connected to the source terminal of the first transistor, the first voltage source and the second voltage source, and the gate terminal of the second transistor is connected to the first voltage source; and

a third transistor having drain, gate and source terminals wherein the drain terminal of the third transistor is connected to the gate terminal of the first transistor, the source terminal of the third transistor is connected to the second voltage source, and the gate terminal of the third transistor is connected to the first voltage source;

a complimentary mirror switched current source circuit coupled to the load to act as a current sink and allowing the switched current source to be a bi-directional current source, wherein the complimentary mirror circuit comprises:

a fourth voltage source;

a fifth voltage source;

a sixth voltage source;

a fourth transistor having drain, gate and source terminals wherein a drain terminal of the fourth transistor is connected to one terminal of the load and a source terminal of the fourth transistor is connected to the sixth voltage source;

a fifth transistor having drain, gate and source terminals wherein the drain terminal of the fifth transistor is connected to the gate terminal of the fourth transistor, the source terminal of the fifth transistor is connected to the fifth voltage source, and the gate terminal of the fifth transistor is connected to the fourth voltage; and

a sixth transistor having drain, gate and source terminals wherein the drain terminal of the sixth transistor is connected to the gate terminal of the fourth transistor, the source terminal of the sixth transistor is connected to the sixth voltage source, and the gate terminal of the sixth transistor is connected to the fourth voltage source;

a first diode having a first terminal connected to the load and a second terminal connected to the drain of the first transistor;

a second diode, a first terminal of the second diode connected to the drain of the fourth transistor and a second terminal of the second diode connected to the load;

a jumper to short the second terminal of the first diode to the first terminal of the second diode together for improved dynamic response;

wherein the third transistor is conducting when the first voltage source is approximately near a source potential of the second transistor causing the first transistor to conduct, a maximum output current through the load controllable by varying the second voltage source;

wherein the fifth transistor is conducting when the fourth voltage source is approximately near zero causing the fourth transistor to conduct, a maximum output current through the load controllable by varying the fifth voltage source.

2. A switched current source in accordance with claim 1 wherein the first transistor, the second transistor and the third transistor are MOSFETS.

3. A switched current source in accordance with claim 1 wherein the second voltage source is used to control a maximum drain current of the first transistor.

4. A switched current source in accordance with claim 3 wherein the first voltage source is used to control a conduction state of the first transistor.

5. A switched current source in accordance with claim 1 wherein the fourth transistor, the fifth transistor and the sixth transistor are MOSFETS.

6. A switched current source in accordance with claim 1 wherein the fifth voltage source is used to control a maximum drain current of the fourth transistor.

7. A switched current source in accordance with claim 6 wherein the fourth voltage source is used to control a conduction state of the fourth transistor.

8. A switched current source in accordance with claim 1 wherein the second voltage source incorporates temperature and process variability.

9. A switched current source in accordance with claim 1 wherein the second and fifth voltage sources incorporates temperature and process variability.

10. A switched current source comprising:

a first voltage source, wherein the first voltage source is an independent controlled voltage source;

a second voltage source;

a third voltage source;

a fourth voltage source, wherein the fourth voltage source is an independent controlled voltage source;

a fifth voltage source;

a sixth voltage source;

a first transistor having a drain terminal connected to one terminal of a load and a source terminal connected to the first voltage source, the second voltage source, and the third voltage source;

a second transistor having drain, gate and source terminals wherein the drain terminal of the second transistor is connected to the gate terminal of the first transistor, the source terminal of the second transistor is connected to the source terminal of the first transistor, the first voltage source and the second voltage source, and the gate terminal of the second transistor is connected to the first voltage source; and

a third transistor having drain, gate and source terminals wherein the drain terminal of the third transistor is connected to the gate terminal of the first transistor, the source terminal of the third transistor is connected to the second voltage source, and the gate terminal of the third transistor is connected to the first voltage source;

a fourth transistor having drain, gate and source terminals wherein a drain terminal of the fourth transistor is connected to one terminal of the load and a source terminal of the fourth transistor is connected to the sixth voltage source;

a fifth transistor having drain, gate and source terminals wherein the drain terminal of the fifth transistor is connected to the gate terminal of the fourth transistor, the source terminal of the fifth transistor is connected to the fifth voltage source, and the gate terminal of the fifth transistor is connected to the fourth voltage; and

a sixth transistor having drain, gate and source terminals wherein the drain terminal of the sixth transistor is connected to the gate terminal of the fourth transistor, the source terminal of the sixth transistor is connected to the sixth voltage source, and the gate terminal of the sixth transistor is connected to the fourth voltage source;

wherein a maximum output current of the first transistor is determined by the second voltage source which is separate from the first voltage source;

wherein a maximum output current of the fourth transistor is determined by the fifth voltage source which is separate from the fourth voltage source;

a first diode having a first terminal connected to the load and a second terminal connected to the drain of the first transistor;

a second diode, a first terminal of the second diode connected to the drain of the fourth transistor and a second terminal of the second diode connected to the load;

a jumper to short the second terminal of the first diode to the first terminal of the second diode together for improved dynamic response.

11. A switched current source in accordance with claim 10 wherein the second and fifth voltage sources incorporates temperature and process variability.

12. A switched current source in accordance with claim 10 wherein the first, second, third, fourth, fifth and sixth transistors are MOSFETS.

13. A switched current source comprising:

a first voltage source;

a second voltage source;

a third voltage source;

a first transistor having a drain terminal coupled to one terminal of a load and a source terminal coupled to the third voltage source;

a second transistor having drain, gate and source terminals wherein the drain terminal of the second transistor is coupled to the gate terminal of the first transistor, the source terminal of the second transistor is coupled to the source terminal of the first transistor, and the gate terminal of the second transistor is coupled to the first voltage source; and

a third transistor having drain, gate and source terminals wherein the drain terminal of the third transistor is coupled to the gate terminal of the first transistor, the source terminal of the third transistor is coupled to the second voltage source, and the gate terminal of the third transistor is coupled to the first voltage source;

a complimentary mirror switched current source circuit coupled to the load to act as a current source and allowing the switched current source to be a bi-directional current source;

a first diode having a first terminal connected to the load and a second terminal connected to the drain of the first transistor;

a second diode, a first terminal of the second diode connected to the drain of a fourth transistor of the complimentary mirror switched current source circuit and a second terminal of the second diode connected to the load; and

a jumper to short the second terminal of the first diode to the first terminal of the second diode together for improved dynamic response.

14. A switched current source in accordance with claim 13 wherein the second voltage source is used to control a maximum drain current of the first transistor.

15. A switched current source in accordance with claim 14 wherein the first voltage source is used to control a conduction state of the first transistor.

Assignments (16)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 059666/0545 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: MICROCHIP TECHNOLOGY INCORPORATED
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041675/0617 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Dec 22, 2014
From: SUPERTEX LLC
To: MICROCHIP TECHNOLOGY INCORPORATED
Reel/Frame 034689/0257 →
CHANGE OF NAME Recorded Dec 19, 2014
From: SUPERTEX, INC.
To: SUPERTEX LLC
Reel/Frame 034682/0134 →