IP Library Granted Patent US 7,635,925
Granted Patent B2
US 7,635,925 · App. 11/538,615 · Granted Dec 22, 2009

Analog combination regulator

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Quick Facts
Patent No.
US 7,635,925
App. No.
11/538,615
Granted
Dec 22, 2009
Kind
B2
Abstract

Methods and apparatus may provide for multiple input voltage regulation in which a current supplied to an output node divides among voltage regulators according to their respective input voltages when the difference in input voltages falls within a voltage range. When the difference in input voltages falls outside of the voltage range, then the current to the output node is supplied substantially through the voltage regulator with the highest input voltage. In some implementations, the voltage range may be determined, at least in part, by a transistor gate-to-source threshold voltage characteristic. In one example, a dual input voltage regulator system in a combination smart card supplies current from contact and/or contactless (e.g., inductively coupled) power sources based on a relative voltage between the respective input voltages.

Claims (33)

1. A system comprising:

a first current path providing a first current I 1 between a first supply node and an output node;

a second current path providing a second current I 2 between a second supply node and the output node; and

a control circuit to regulate a voltage at the output node by supplying a control signal to each current path, the control circuit being operable to divide a current supplied to the output nodes along said current paths when a difference between a voltage at the first supply node and a voltage at the second supply node falls within a voltage range, the division defined by a function characterized by three regions bound by two threshold voltage levels including a first, second and third region where

I 1 >I 2 in the first region,

I 1 =I 2 in the second region, and

I 1 <I 2 in the third region,

and otherwise to supply substantially all the output current from the supply node with the higher voltage.

2. The system of claim 1 , wherein current supplied to the output node transitions substantially smoothly from the first current path to the second current path as voltage at the second supply node increases within the voltage range.

3. The system of claim 1 , wherein current supplied to the output node transitions substantially smoothly from the second current path to the first current path as voltage at the first supply node increases within the voltage range.

4. The system of claim 1 , wherein the control circuit divides the current by supplying the control signal to bias a transistor in one of the current paths.

5. The system of claim 4 , wherein the first current path comprises a first PMOS transistor having a source terminal connected to the first supply node.

6. The system of claim 5 , wherein the second current path comprises a second PMOS transistor having a source terminal connected to the second supply node.

7. The system of claim 6 , wherein the output node connects to a drain terminal of the first PMOS transistor in the first current path and to a drain terminal of the second PMOS transistor in the second current path.

8. The system of claim 7 , wherein the control circuit provides a bias signal to modulate the first and second PMOS transistors.

9. The system of claim 6 , further comprising gate bias circuits to supply substantially a same voltage to a gate terminal of the first PMOS transistor and to a gate terminal of the second PMOS transistor when the difference is characterized by the second region.

10. The system of claim 1 , further comprising a smart card including the first current path, the second current path, and the controller.

11. The system of claim 1 , wherein the voltage range spans up to about 1 Volt.

12. The system of claim 1 , wherein the voltage range spans between about 0.2 Volts and about 0.8 Volts.

13. The system of claim 1 , wherein the first current path and the second current path each comprise a junction field effect transistor.

14. The system of claim 1 , wherein the first current path and the second current path each comprise a bipolar junction transistor.

15. A method comprising:

receiving a first voltage at a first input of a voltage regulator;

receiving a second voltage at a second input of the voltage regulator;

regulating a voltage at an output of the voltage regulator; and

supplying current to the output substantially only from an input with a higher input voltage when a difference between the first voltage and the second voltage falls outside of a voltage range, and supplying current to the output such that a current supplied from each of the first and second inputs divides according to voltages at their respective inputs when a difference between the first and second voltage falls within the voltage range.

16. The method of claim 15 , wherein the voltage range depends substantially on a gate-to-source threshold voltage of a transistor.

17. The method of claim 15 , wherein the voltage range comprises a voltage difference between a first trigger and a second trigger where each trigger defines a transitional threshold from supplying current from only one input to supplying at least a portion of current from both the first and second input, the difference selected from of a group consisting of: about 0.1, about 0.2, about 0.3, about 0.4, about 0.5, about 0.6, about 0.7, about 0.8, about 0.9, and about 1.0 Volts.

18. The method of claim 15 , further comprising supplying power to the first input through physical contact with a connector.

19. The method of claim 15 , further comprising supplying power to the second input through a wireless interface.

20. The method of claim 15 , further comprising transferring data through an interface operable to receive the first voltage.

21. The method of claim 20 , further comprising transferring data through an interface operable to receive the second voltage.

22. The method of claim 15 , further comprising selecting a highest available voltage at the first and second inputs to bias a substrate of a transistor in the voltage regulator.

Assignments (17)
RELEASE OF SECURITY INTEREST Recorded Mar 14, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 060894/0437 →
RELEASE OF SECURITY INTEREST Recorded Mar 11, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059363/0001 →
RELEASE OF SECURITY INTEREST Recorded Mar 10, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059863/0400 →
RELEASE OF SECURITY INTEREST Recorded Mar 9, 2022
From: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059358/0001 →
RELEASE OF SECURITY INTEREST Recorded Feb 28, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: ATMEL CORPORATION
Reel/Frame 059262/0105 →
RELEASE OF SECURITY INTEREST Recorded Feb 25, 2022
From: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 059333/0222 →
SECURITY INTEREST Recorded Jun 4, 2021
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 057935/0474 →
SECURITY INTEREST Recorded Dec 24, 2020
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS COLLATERAL AGENT
Reel/Frame 055671/0612 →
SECURITY INTEREST Recorded Jun 5, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION
Reel/Frame 053468/0705 →
RELEASE OF SECURITY INTEREST Recorded May 30, 2020
From: JPMORGAN CHASE BANK, N.A, AS ADMINISTRATIVE AGENT
To: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
Reel/Frame 053466/0011 →
SECURITY INTEREST Recorded Apr 24, 2020
From: MICROCHIP TECHNOLOGY INC.; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 053311/0305 →
SECURITY INTEREST Recorded Sep 18, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: WELLS FARGO BANK, NATIONAL ASSOCIATION, AS NOTES COLLATERAL AGENT
Reel/Frame 047103/0206 →
SECURITY INTEREST Recorded Jun 25, 2018
From: MICROCHIP TECHNOLOGY INCORPORATED; SILICON STORAGE TECHNOLOGY, INC.; ATMEL CORPORATION; MICROSEMI CORPORATION; MICROSEMI STORAGE SOLUTIONS, INC.
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 046426/0001 →
SECURITY INTEREST Recorded Feb 10, 2017
From: ATMEL CORPORATION
To: JPMORGAN CHASE BANK, N.A., AS ADMINISTRATIVE AGENT
Reel/Frame 041715/0747 →
TERMINATION AND RELEASE OF SECURITY INTEREST IN PATENT COLLATERAL Recorded Apr 7, 2016
From: MORGAN STANLEY SENIOR FUNDING, INC.
To: ATMEL CORPORATION
Reel/Frame 038376/0001 →
PATENT SECURITY AGREEMENT Recorded Jan 3, 2014
From: ATMEL CORPORATION
To: MORGAN STANLEY SENIOR FUNDING, INC. AS ADMINISTRATIVE AGENT
Reel/Frame 031912/0173 →
ASSIGNMENT OF ASSIGNOR'S INTEREST Recorded Oct 5, 2006
From: FREW, LOUIS; BATES, COLIN
To: ATMEL CORPORATION
Reel/Frame 018354/0862 →