Protruding spacers for self-aligned contacts
View Patent ↗A protruding spacer that protrudes above the top surface of a gate electrode structure provides enhanced resistance to exposure of the gate electrode during the etch process used to form self-aligned contacts. The protruding spacer may be formed using an amorphous carbon sacrificial layer as the top layer of the patterned gate electrode structure. Dielectric spacers are formed alongside the gate electrode structure, including alongside the sacrificial amorphous carbon layer. The dielectric spacers extend substantially to the top of the amorphous carbon layer. The amorphous carbon layer is then removed such that the remaining gate structure includes dielectric spacers that have a protruding section that protrudes above the top surface of the remaining gate structure. A nitride layer may be formed over the gate structure. Such a structure prevents exposure of the gate electrode during the formation of self-aligned contacts, and shorting, once the contact openings are filled.
1. A semiconductor product comprising a gate structure formed over a semiconductor substrate, said gate structure having a pair of opposed sidewalls and a first height, and a pair of dielectric spacers, each spacer extending along a respective sidewall and having a spacer height;
wherein the spacer height exceeds the first height by approximately a thickness of a sacrificial layer previously formed over the gate structure; and
wherein the previously formed sacrificial layer comprised amorphous carbon.
2. The semiconductor product as in claim 1 , wherein said gate structure includes an upper surface and each of said spacers protrudes above said upper surface, the previously formed sacrificial layer having been formed on the upper surface.
3. The semiconductor product as in claim 2 , wherein each of said spacers protrudes above said upper surface by a distance ranging from approximately 500 angstroms to approximately 2000 angstroms.
4. The semiconductor product as in claim 2 , in which said gate structure includes a gate electrode layer and a hardmask layer disposed thereover, said upper surface being a surface of said hardmask layer.
5. The semiconductor product as in claim 1 , in which said spacers each include a generally planar inner surface that forms a conterminous portion with said respective sidewall, and each spacer includes a protruding portion that extends above said respective sidewall.
6. The semiconductor product as in claim 1 , further comprising a nitride layer formed thereover.
7. A semiconductor product comprising:
a gate structure formed over a semiconductor substrate, the gate structure having at least one sidewall and a first height; and,
at least one dielectric spacer extending along the sidewall and having a spacer height;
wherein the spacer height exceeds the first height by approximately a thickness of a sacrificial layer previously formed over the gate structure; and
wherein the previously formed sacrificial layer was a layer comprising amorphous carbon.
8. The semiconductor product of claim 7 , wherein the spacer height exceeds the first height by approximately 500 angstroms to approximately 2000 angstroms.
9. The semiconductor product of claim 7 , wherein the gate structure includes an upper surface, the previously formed sacrificial layer having been formed on the upper surface.
10. The semiconductor product of claim 9 , in which the gate structure includes a gate electrode layer and a hardmask layer disposed thereover, the upper surface being a surface of the hardmask layer.
11. The semiconductor product of claim 7 , wherein the sidewall includes a generally planar inner surface that forms a conterminous portion with the sidewall, and the spacer includes a protruding portion that extends above the sidewall.
12. The semiconductor product of claim 7 , further comprising a nitride layer formed thereover.
13. A semiconductor product comprising a gate structure formed over a semiconductor substrate, the gate structure having a pair of opposed sidewalls and a first height, and a pair of dielectric spacers, each spacer extending along a respective sidewall and having a spacer height;
wherein the gate structure comprises a gate electrode layer and a hardmask layer disposed thereover; and
wherein the spacer height exceeds the first height by approximately a thickness of a sacrificial layer previously formed over an upper surface of the hardmask layer.
14. The semiconductor product as in claim 13 , wherein each of the spacers protrudes above said upper surface by a distance ranging from approximately 500 angstroms to approximately 2000 angstroms.
15. The semiconductor product as in claim 13 , in which said spacers each include a generally planar inner surface that forms a conterminous portion with said respective sidewall, and each spacer includes a protruding portion that extends above said respective sidewall.
16. The semiconductor product as in claim 13 , further comprising a nitride layer formed over the gate structure.
17. A semiconductor product comprising:
a gate structure, comprising a gate electrode layer and a hardmask layer disposed thereover, formed over a semiconductor substrate, the gate structure having at least one sidewall and a first height; and,
at least one dielectric spacer extending along the sidewall and having a spacer height;
wherein the spacer height exceeds the first height by approximately a thickness of a sacrificial layer previously formed over an upper surface of the hardmask layer.
18. The semiconductor product of claim 17 , wherein the spacer height exceeds the first height by approximately 500 angstroms to approximately 2000 angstroms.
19. The semiconductor product of claim 17 , wherein the sidewall includes a generally planar inner surface that forms a conterminous portion with the sidewall, and the spacer includes a protruding portion that extends above the sidewall.
20. The semiconductor product of claim 17 , further comprising a nitride layer formed over the gate structure.