Stackable integrated circuit structures and systems devices and methods related thereto
View Patent ↗An apparatus and a method for packaging semiconductor devices. The apparatus is a three-dimensional electronic package comprising one or more electronic components, a plurality of electrical contact pads, and a plurality of electrically conductive three-dimensional plugs formed through an encapsulant. Specific ones of the plurality of electrical contact pads are electrically coupled to the one or more electronic components on an uppermost surface of the plurality of electrical contact pads. The encapsulant is formed over and covers the one or more electronic devices. The plurality of three-dimensional plugs have a first end extending from at least the uppermost portion of one or more of the plurality of electrical contact pads and a second end extending substantially to an uppermost surface of the encapsulant.
1. An integrated circuit structure, comprising:
a sacrificial base layer;
a plurality of electronic components located on the sacrificial base layer;
a plurality of electrical contact pads each electrically coupled to the plurality of electronic components on an uppermost surface of each of the plurality of electrical contact pads;
an encapsulant covering the plurality of electronic components; and
a plurality of electrically conductive three-dimensional plugs, each having a lowermost surface extending through one or more of the plurality of electrical contact pads to electrically couple the plurality of electrically conductive three-dimensional plugs to one or more of the plurality of electrical contact pads.
2. The integrated circuit structure of claim 1 , wherein the plurality of electrically conductive three-dimensional plugs are comprised of copper or a copper alloy.
3. The integrated circuit structure of claim 1 , wherein the plurality of electrically conductive three-dimensional plugs are solid.
4. The integrated circuit structure of claim 1 , wherein the plurality of electrical contact pads are formed from a plated-up metal layer.
5. The integrated circuit structure of claim 4 , wherein the plated-up metal layer comprises a gold-nickel composite.
6. The integrated circuit structure of claim 1 , wherein one end of each of the plurality of three-dimensional plugs extends substantially to an uppermost surface of the encapsulant.
7. The integrated circuit structure of claim 1 , wherein the sacrificial base strip comprises a non-conductive material.
8. An integrated circuit structure, comprising:
an integrated circuit structure matrix including a plurality of three-dimensional stacked integrated circuit packages, each of the three-dimensional stacked integrated circuit packages comprising:
a plurality of integrated circuit structures, each including:
a plurality of electronic components;
a plurality of electrical contact pads each electrically coupled to the plurality of electronic components on an uppermost surface of each of the electrical contact pads;
an encapsulant covering the plurality of electronic components; and
a plurality of electrically conductive three-dimensional plugs, each having a lowermost surface extending through one or more of the plurality of electrical contact pads to electrically couple the plurality of electrically conductive three-dimensional plus to one or more of the electrical contact pads, wherein the three-dimensional stacked integrated circuit packages are free of a base strip and are stacked, one on top of another.
9. The integrated circuit structure of claim 8 , wherein one or more of the plurality of electrically conductive three-dimensional plugs has a lowermost surface defined by an uppermost surface of the plurality of electrical contact pads.
10. The integrated circuit structure of claim 8 , further comprising one or more four layer thin core substrates, system-in-package modules or combinations thereof, each stacked on the integrated circuit structure.
11. An electronic device, comprising:
an integrated circuit structure matrix including a plurality of three-dimensional stacked integrated circuit packages, each of the three-dimensional stacked integrated circuit packages comprising:
a plurality of electronic components;
a plurality of electrical contact pads each electrically coupled to the plurality of electronic components on an uppermost surface of each of the electrical contact pads;
an encapsulant covering the plurality of electronic components; and
a plurality of electrically conductive three-dimensional plugs, each having a lowermost surface extending through one or more of the plurality of electrical contact pads to electrically couple the plurality of electrically conductive three-dimensional plus to one or more of the electrical contact pads, wherein the three-dimensional stacked integrated circuit packages are free of a base strip and are stacked, one on top of another.
12. The electronic device of claim 11 , wherein one or more of the plurality of electrically conductive three-dimensional plugs has a lowermost surface defined by an uppermost surface of the plurality of electrical contact pads.
13. The electronic device of claim 11 , wherein a first three-dimensional stacked integrated circuit package is electrically coupled to a second three-dimensional stacked integrated circuit package with solder, conductive epoxy or metal bonding.
14. The electronic device of claim 11 , wherein more than two three-dimensional stacked integrated circuit packages are stacked.
15. A system comprising:
an integrated circuit structure matrix including a plurality of three-dimensional stacked integrated circuit packages, each of the three-dimensional stacked integrated circuit packages comprising:
a plurality of electronic components;
a plurality of electrical contact pads each electrically coupled to the plurality of electronic components on an uppermost surface of each of the electrical contact pads;
an encapsulant covering the plurality of electronic components; and
a plurality of electrically conductive three-dimensional plugs, each having a lowermost surface extending through one or more of the plurality of electrical contact pads to electrically couple the plurality of electrically conductive three-dimensional plus to one or more of the electrical contact pads, wherein the three-dimensional stacked integrated circuit packages are free of a base strip and are stacked, one on top of another; and
one or more four-layer thin core substrates, system-in-package (SIP) modules or combinations thereof each stacked on the integrated circuit structure.
16. The system of claim 15 , wherein one or more of the plurality of electrically conductive three-dimensional plugs has a lowermost surface defined by an uppermost surface of the plurality of electrical contact pads.
17. The system of claim 15 , wherein each of the one or more four-layer thin core substrates includes a core comprising epoxy laminate or ceramic.
18. The system of claim 15 , wherein the SIP module includes a package selected from a ball-grid array, a quad flat-pack no-lead and a quad flat package.
19. A method of making an integrated circuit structure, comprising:
providing a sacrificial base layer;
locating a plurality of electronic components on the sacrificial base layer;
electrically coupling an uppermost surface of each of a plurality of electrical contact pads to the plurality of electronic components, wherein the lowermost surface of each of the plurality of electrical contact pads defines a lowermost surface of a plurality of electrically conductive three-dimensional plugs;
covering the plurality of electronic components with an encapsulant; and
electrically coupling the plurality of electrical conductive three-dimensional plugs to one or more of the plurality of electrical contact pads, wherein each of the plurality of electrically conductive three-dimensional plugs has a lowermost surface extending through one or more of the plurality of electrical contact pads.
20. The method of claim 19 further comprising removing the sacrificial base layer.
21. The method of claim 20 further comprising stacking the integrated circuit structure with another integrated circuit structure.
22. A packaged product produced according to the method of claim 19 .
23. A packaged product produced according to the method of claim 21 .