Method of evaluating the uniformity of the thickness of the polysilicon gate layer
View Patent ↗A method of evaluating the uniformity of the thickness of the polysilicon gate layer is provided. A substrate having a dense trenches area and a sparse trenches area is provided. A plurality of first trench isolation structures are formed in the sparse trenches area of the substrate and a plurality of second trench isolation structures are simultaneously formed in the dense trenches area of the substrate. A mask layer is formed between the gaps of the first and the second trench isolation structures. A portion of the first trench isolation structures of the sparse trenches area is then removed. Then, the mask layer is removed until the surface of the substrate is exposed. A polysilicon gate layer is formed over the substrate. Finally, a planarization process is performed to remove a portion of the polysilicon gate layer.
1. A method of evaluating the uniformity of the thickness of the polysilicon gate layer, comprising:
providing a substrate having a dense trenches area and a sparse trenches area;
forming a plurality of first trench isolation structures in the dense trenches area of the substrate and simultaneously forming a plurality of second trench isolation structures in the sparse trenches area of the substrate, wherein a mask layer is formed between the gaps of the first trench isolation structures and the second trench isolation structures;
removing portions of the first trench isolation structures of the dense trenches area to make the top surface of the first trench isolation structures lower than that of the second trench isolation structures;
removing the mask layer until the surface of the substrate is exposed;
forming a polysilicon gate layer to cover the substrate, the first trench isolation structures and the second trench isolation structures; and
performing a planarization process for removing portions of the polysilicon gate layer.
2. The method of claim 1 , wherein the method for removing portions of the first trench isolation structures of the dense trenches area comprises:
forming a photoresist layer to cover the sparse trenches area of the substrate; and
etching the first trench isolation structures located in the dense trenches area by using the photoresist layer as a mask.
3. The method of claim 1 , wherein the planarization process comprises polysilicon chemical mechanical polishing process.
4. The method of claim 1 , wherein the material of the mask layer comprises silicon nitride.
5. The method of claim 1 , wherein the method of forming the polysilicon gate layer is a chemical vapor deposition process.
6. The method of claim 1 , further comprising forming a pad oxide layer between the substrate and the mask layer.
7. The method of claim 6 , wherein the material of the pad oxide layer comprises silicon oxide.
8. The method of claim 1 , wherein the dense trenches area comprises a memory cell area and the sparse trenches area comprises a peripheral circuit area.