Method and apparatus for reducing electrical interconnection fatigue
View Patent ↗A method and apparatus is provided that pertains to resisting crack initiation and propagation in electrical interconnections between components and substrates in ball grid array microelectronic packages. A hybrid of dielectric defined and non-dielectric defined electrical interconnects reduces the potential for electrical interconnection failure without having to control the dielectric defined interconnect ratio of substrates. In addition selective orientation of the dielectric defined edge portion of the electrical interconnect away from the point where cracks initiate resists crack propagation and component failure.
1. An electronic assembly, comprising:
a system substrate;
a microelectronic package electrically interconnected with the system substrate, the microelectronic package further comprising:
a microelectronic die; and
a substrate, the substrate further comprising an array having a plurality electrical interconnects on a surface of the substrate, the array having an outer portion and a center, and a dielectric layer, wherein the dielectric layer covers a portion of the surface of the substrate and contacts no more than a portion of an edge of at least one of the electrical interconnects to define a dielectric electrical interconnect edge portion and a non-dielectric electrical interconnect edge portion, the non-dielectric electrical interconnect edge portion being oriented on the surface of the substrate to resist crack propagation.
2. The substrate of claim 1 , wherein the non-dielectric electrical interconnect edge portion is oriented distal to the center to resist inward crack propagation.
3. The substrate of claim 1 , wherein the non-dielectric electrical interconnect edge portion is oriented proximal to the center to resist outward crack propagation.
4. The substrate of claim 1 , wherein the ratio of the dielectric defined edge portion to the non-dielectric defined edge portion is greater than one.
5. The substrate of claim 1 , wherein the ratio of the dielectric defined edge portion to the non-dielectric defined edge portion is less than one.
6. The substrate of claim 1 , further comprising a corresponding via and a corresponding linking interconnect for each electrical interconnect, the electrical interconnect being spaced apart from the corresponding via a predetermined distance, the corresponding linking interconnect electrically interconnecting the electrical interconnect to the corresponding via.
7. The substrate of claim 6 , wherein the corresponding via is oriented between the electrical interconnect and the center of the array.
8. The substrate of claim 6 , wherein the electrical interconnect is oriented between the corresponding via and the center of the array.