Apparatus and method of error detection and correction in a radiation-hardened static random access memory field-programmable gate array
View Patent ↗The present system comprises a radiation tolerant programmable logic device having logic modules and routing resources coupling together the logic modules. Configuration data lines providing configuration data control the programming of the logic modules and the routing resources. Error correction circuitry coupled to the configuration data lines analyzes and corrects any errors in the configuration data that may occur due to a single event upset (SEU).
1. A method for providing a radiation tolerant programmable logic device, said method comprising:
providing logic modules;
providing routing resources coupling said logic modules;
providing configuration data lines having configuration data controlling said logic modules and said routing resources; and
providing error correction circuitry coupled to said configuration data lines, wherein said error correction circuitry analyzes and corrects errors in said configuration data, and wherein said error correction circuitry comprises a radiation tolerant read/write amplifier and a radiation tolerant shift register coupled to said radiation tolerant read/write amplifier.
2. The method of claim 1 , wherein said error correction circuitry further comprises:
a voting block coupled between said radiation tolerant read/write amplifier and said configuration data line.
3. The method of claim 2 , wherein said error correction circuitry further comprises a plurality of latches having at least one transistor large enough to withstand a Q crit or larger particle strike, said latches coupled to said voting block.
4. The method of claim 1 , wherein said error correction circuitry further comprises:
a plurality of electronic code correction (ECC) latches each having a plurality of inputs and an output;
a first multiplexer having an input and a plurality of outputs;
a voting logic circuit having inputs coupled to at least one output of said plurality of ECC latches and coupled to at least one of said outputs of said multiplexer and said voting logic circuit having an output coupled to first input of a two-input multiplexer;
said radiation tolerant shift register coupled to one of said plurality of outputs of said first multiplexer and an output coupled to a second input of said two-input multiplexer;
a write latch having an input coupled to an output of said two-input multiplexer; and
said radiation tolerant read/write amplifier having an input coupled to an output of said write latch and at lease one of said plurality of outputs of said first multiplexer.
5. The method of claim 4 , wherein said voting logic circuit further comprises:
three two-input AND gates; and
a three-input AND gate having inputs coupled to an output of each of said three two-input AND gates.
6. The method of claim 4 , wherein said read and write amplifier further comprises:
a write amplifier circuit having a plurality of inputs and a plurality of outputs;
a precharge circuit coupled to said input of said write amplifier circuit and having a plurality of outputs; and
a sense circuit having inputs coupled to said outputs of said write amplifier circuit and said outputs of said precharge circuit and having an output.
7. The method of claim 4 , wherein said ECC latches further comprise:
a first transistor of a first nominal size having an source coupled to a first node forming an input to said ECC latch, a drain coupled to a second node and a gate coupled to a logic module signal line;
a second transistor of a nominal size having an source coupled to said first node, a drain coupled to said second node and a gate coupled to an inverted logic module signal line;
a first two-input NAND gate having a first input coupled to said second node and a second input coupled to a reset signal line;
a second two-input NAND gate having a first input coupled to an output of first two-input NAND gate and a second input coupled to a set signal line and having an output to said output of said ECC latch;
a third transistor of second larger size having a source coupled to a third node, a drain coupled to a fourth node and a gate coupled to a second logic module signal line; and
a fourth transistor of second larger size having a source coupled to said third node, said third coupled to said output of said second two-input NAND gate, a drain coupled to said forth node, said fourth node coupled to said first input of said first two-input NAND gate, and a gate coupled to a second inverted logic module signal line.