Flash/dynamic random access memory field programmable gate array
View Patent ↗A circuit for selectively interconnecting two nodes in an integrated circuit device includes a memory array having a plurality of wordlines and a plurality of bitlines. A refresh transistor has a source coupled to one of the plurality of bitlines, a control gate coupled to a dynamic random access memory wordline and a drain. A switching transistor has a gate coupled to the drain of the refresh transistor, a source coupled to a first one of the nodes and a drain coupled to a second one of the nodes. An address decoder for supplies periodic signals to the wordlines and the dynamic random access memory wordline.
1. A method for interconnecting two nodes in an integrated circuit device comprising:
storing a charge representing an on-status bit on a gate capacitance of a switching transistor coupled between the two nodes; and
periodically refreshing said charge, wherein periodically refreshing said charge is performed at a periodic interval that is a function of temperature of a die on which said circuit is disposed and comprises periodically coupling a voltage representing said on-status bit to said gate capacitance of said switching transistor through a refresh transistor.
2. The method of claim 1 , wherein coupling a voltage representing said on-status bit comprises:
retrieving a signal representing said on-status bit from a memory; and
converting said signal into said voltage.
3. The method of claim 1 , wherein said switching transistor comprises a gate coupled to the drain of said refresh transistor, a source coupled to one of the two nodes, and a drain coupled to the other of the two nodes.
4. The method of claim 1 , wherein said refresh transistor comprises a source coupled to one of a plurality of bitlines, a control gate coupled to one of a plurality of dynamic random access memory wordlines, and a drain.
5. A method for interconnecting N pairs of nodes in an integrated circuit device comprising:
for each of said N pairs of nodes, storing a charge representing an on-status bit on a gate capacitance of a switching transistor coupled between the pair of nodes; and
periodically refreshing each said charge, wherein periodically refreshing said charge is performed at a periodic interval that is a function of temperature of a die on which said circuit is disposed and comprises periodically coupling a voltage representing said on-status bit to said gate capacitance of each said switching transistor through a separate refresh transistor.
6. The method of claim 5 , wherein periodically coupling a voltage comprises periodically coupling a voltage having a magnitude sufficient to turn on each said switching transistor without a Vth drop.
7. The method of claim 5 , wherein coupling a voltage representing said on-status bit comprises:
retrieving a signal representing said on-status bit from a memory; and
converting said signal into said voltage.
8. The method of claim 5 , wherein said switching transistor comprises a gate coupled to the drain of said separate refresh transistor, a source coupled to one of the nodes in the pair of nodes, and a drain coupled to the other node in the pair of nodes.
9. The method of claim 5 , wherein said separate refresh transistor comprises a source coupled to one of a plurality of bitlines, a control gate coupled to one of a plurality of dynamic random access memory wordlines, and a drain.