Embedded memory in a CMOS circuit and methods of forming the same

1. A memory circuit comprising:

a gate layer formed on a substrate;

a dielectric layer formed over the gate layer;

a first metal layer formed on an upper surface of the dielectric layer;

a via opening extending from the upper surface of the dielectric layer to the gate layer; and

a two-terminal memory element formed in the via opening and comprising a diode-based memory element; and

a CMOS transistor formed on the substrate and adapted to program the two-terminal memory element;

wherein the two-terminal memory element is formed between the gate layer and the first metal layer.

2. The memory circuit of claim 1 wherein the two-terminal memory element is positioned laterally adjacent to the CMOS transistor.

3. The memory circuit of claim 1 wherein the two-terminal memory element is formed on an isolation region of the substrate that isolates a first terminal of the memory element from the CMOS transistor.

4. The memory circuit of claim 1 , wherein the diode-based memory element comprises:

a first conductor;

a second conductor formed above the first conductor; and

a vertically oriented junction diode disposed between the first and second conductors.

5. The memory circuit of claim 4 , wherein the vertically oriented junction diode is formed from polysilicon and includes a deposition induced central grain boundary that getters defects.

6. The memory circuit of claim 4 wherein the first conductor is at a level of a gate layer of the CMOS transistor.

7. The memory circuit of claim 6 wherein the first conductor is formed from the gate layer used to form the CMOS transistor.

8. The memory circuit of claim 4 wherein the first conductor comprises doped polysilicon.

9. The memory circuit of claim 8 wherein the first conductor forms part of the vertically oriented junction diode.

10. The memory circuit of claim 4 wherein the second conductor is formed from the first metal layer.

11. The memory circuit of claim 10 wherein the first metal layer defines a bit line of the memory circuit.

12. The memory circuit of claim 4 wherein:

the vertically oriented junction diode comprises a vertically oriented polysilicon diode; and

at least one of the first and second conductors comprises a barrier/liner layer.

13. The memory circuit of claim 12 wherein the vertically oriented polysilicon diode comprises a p-i-n diode.

14. The memory circuit of claim 4 further comprising an antifuse layer disposed below the second conductor.

15. The memory circuit of claim 14 wherein the antifuse layer comprises at least one of silicon dioxide, silicon nitride and silicon oxynitride.

16. The memory circuit of claim 1 wherein the two-terminal memory element has a width of less than about 800 nanometers.

17. The memory circuit of claim 1 further comprising a plurality of two-terminal memory elements formed on the substrate and wherein each two-terminal memory element is formed between the gate layer and the first metal layer of the memory circuit.

18. The memory circuit of claim 17 wherein the two-terminal memory elements have a pitch of less than about 1.75 microns.

19. The memory circuit of claim 17 wherein each two-terminal memory element has a width of less than about 800 nanometers.

20. The memory circuit of claim 17 wherein each two-terminal memory element comprises a programmable read only memory (PROM) or a re-writable memory.

21. The memory circuit of claim 20 wherein each two-terminal memory element comprises a diode-based memory element.

22. The memory circuit of claim 21 wherein each diode-based memory element comprises:

a first conductor;

a second conductor formed above the first conductor; and

a vertically oriented junction diode disposed between the first and second conductors.

23. The memory circuit of claim 22 wherein the first conductor of each diode-based memory element is at a level of a gate layer of the CMOS transistor.

24. The memory circuit of claim 23 wherein the first conductor of each diode-based memory element is formed from the gate layer used to form the CMOS transistor.

25. The memory circuit of claim 22 wherein the second conductor of each diode-based memory element is formed from the first metal layer.

26. The memory circuit of claim 25 wherein the first metal layer defines a bit line of the memory circuit.

27. The memory circuit of claim 1 wherein the CMOS transistor comprises:

a well region;

an isolation region formed in the well region so as to form a first portion and a second portion of the well region;

a channel region formed adjacent to the first portion of the well region;

a gate dielectric layer formed over at least a portion of the isolation region, at least a portion of the channel region and the first portion of the well region;

a gate electrode formed on the gate dielectric;

a drain region formed in the second portion of the well region; and

a drain contact that extends from the drain region to the first metal layer of the memory circuit.

28. The memory circuit of claim 1 wherein the CMOS transistor comprises at least one extended lightly doped drain (LDD) region.

29. The memory circuit of claim 1 wherein the CMOS transistor is further adapted to program the two-terminal memory element to store data.

30. The memory circuit of claim 1 , wherein the two-terminal memory element comprises a programmable read only memory (PROM) or a re-writable memory.