Embedded memory in a CMOS circuit and methods of forming the same

1. A method of forming a memory circuit, the method comprising:

forming a gate layer on a substrate;

forming a dielectric layer over the gate layer;

forming a via opening in the dielectric layer to expose the gate layer, wherein the via opening extends from an upper surface of the dielectric layer to the gate layer;

forming a two-terminal memory element in the via opening, the two-terminal memory element comprising a diode and having a first electrode formed from the gate layer;

forming a first metal layer directly on the upper surface of the dielectric layer, and wherein the two terminal memory element is formed between the gate layer and the first metal layer; and

forming a CMOS transistor on the substrate, the CMOS transistor for programming the two-terminal memory element, the CMOS transistor having a gate electrode formed from the gate layer.

2. The method of claim 1 wherein forming the two-terminal memory element comprises forming the two-terminal memory element adjacent to the CMOS transistor.

3. The method of claim 1 wherein forming the two-terminal memory element comprises forming the two-terminal memory element on an isolation region of the substrate that isolates a first terminal of the memory element from the CMOS transistor.

4. The method of claim 1 wherein forming the two-terminal memory element comprises forming a programmable read only memory (PROM) element or a re-writable memory element.

5. The method of claim 4 wherein the diode comprises a vertically oriented diode.

6. The method of claim 1 wherein forming the two-terminal memory element comprises:

forming a first conductor;

forming a vertically oriented diode above the first conductor; and

forming a second conductor above the vertically oriented diode.

7. The method of claim 6 wherein forming the first conductor comprises forming the first conductor at a level of a gate layer of the CMOS transistor.

8. The method of claim 7 wherein forming the first conductor comprises forming the first conductor from the gate layer used to form the CMOS transistor.

9. The method of claim 6 wherein forming the first conductor comprises depositing and patterning polysilicon.

10. The method of claim 9 wherein forming the first conductor comprises forming at least a part of the vertically oriented diode.

11. The method of claim 6 wherein forming the second conductor comprises forming from the first metal layer.

12. The method of claim 11 further comprising forming a bit line of the memory circuit from the first metal layer.

13. The method of claim 6 wherein:

forming the vertically oriented diode comprises forming a vertically oriented polysilicon diode; and

forming at least one of the first and second conductors comprises forming a barrier/liner layer.

14. The method of claim 13 wherein forming the vertically oriented polysilicon diode comprises forming a p-i-n diode.

15. The method of claim 6 further comprising forming an antifuse layer disposed below the second conductor.

16. The method of claim 15 wherein forming the antifuse layer comprises forming at least one of silicon dioxide, silicon nitride and silicon oxynitride.

17. The method of claim 6 wherein forming the vertically oriented diode comprises depositing polysilicon so as to form a deposition induced central grain boundary that getters defects.

18. The method of claim 1 further comprising forming a plurality of two-terminal memory elements on the substrate between the gate layer and the first metal layer of the memory circuit.

19. The method of claim 1 wherein forming the CMOS transistor comprises:

forming a well region in the substrate;

forming an isolation region in the well region so as to form a first portion and a second portion of the well region;

forming a channel region adjacent to the first portion of the well region;

forming a gate dielectric layer over at least a portion of the isolation region, at least a portion of the channel region and the first portion of the well region;

forming a gate electrode on the gate dielectric;

forming a drain region in the second portion of the well region; and

forming a drain contact that extends from the drain region to the first metal layer of the memory circuit.

20. The method of claim 1 wherein forming the CMOS transistor comprises forming at least one extended lightly doped drain (LDD) region in an active region of the substrate.

21. A method of forming a memory circuit, the method comprising:

forming a gate layer on a substrate;

forming a dielectric layer over the gate layer;

forming a via opening in the dielectric layer to expose the gate layer, wherein the via opening extends from an upper surface of the dielectric layer to the gate layer;

forming a two-terminal memory element in the via opening, the two-terminal memory element comprising a diode and having a first electrode formed from the gate layer;

forming a first metal layer directly on the upper surface of the dielectric layer, and wherein the two terminal memory element is formed between the gate layer and the first metal layer; and

forming a CMOS transistor on the substrate for programming the two-terminal memory element, the CMOS transistor having a gate electrode formed from the gate layer deposited on the substrate.

22. The method of claim 21 further comprising forming a plurality of two-terminal memory elements on the substrate each having a first electrode formed from the gate layer used to form the gate electrode of the CMOS transistor.

23. The method of claim 21 wherein the diode comprises forming a vertically oriented diode.

24. The method of claim 21 wherein forming the two-terminal memory element comprises forming an antifuse coupled to a junction diode.

25. The method of claim 21 further comprising:

coupling a drain region of the CMOS transistor to the first metal layer; and

forming a second electrode of each two-terminal memory element from the first metal layer.

26. The method of claim 25 further comprising forming a bit line from the first metal layer.

27. The method of claim 21 wherein forming the CMOS transistor comprises:

forming a well region in the substrate;

forming an isolation region in the well region so as to form a first portion and a second portion of the well region;

forming a channel region adjacent to the first portion of the well region;

forming a gate dielectric over at least a portion of the isolation region, at least a portion of the channel region and the first portion of the well region;

forming the gate electrode on the gate dielectric;

forming a drain region in the second portion of the well region; and

forming a drain contact that extends from the drain region to a first metal layer of the memory circuit.

28. The method of claim 21 wherein forming the CMOS transistor comprises forming at least one extended lightly doped drain (LDD) region in an active region of the substrate.

29. A method of forming a memory circuit, the method comprising:

forming a gate layer on a substrate;

forming a dielectric layer over the gate layer;

forming a plurality of via openings in the dielectric layer to expose the gate layer, wherein each via opening extends from an upper surface of the dielectric layer to the gate layer;

forming a plurality of two-terminal memory elements on a substrate, each two-terminal memory element formed in a corresponding one of the via openings and comprising a diode, each two-terminal memory element further having a first electrode and a second electrode;

forming a first metal layer directly on the upper surface of the dielectric layer, and wherein each two terminal memory element is formed between the gate layer and the first metal layer; and

forming a CMOS transistor on the substrate for programming the two-terminal memory elements, the CMOS transistor having:

a gate electrode formed from the gate layer deposited on the substrate;

a drain region; and

a drain contact that extends from the drain region to the first metal layer of the memory circuit;

wherein the first electrode of each two-terminal memory element is formed from the gate layer used to form the gate electrode of the CMOS transistor and the second electrode of each two-terminal memory element is formed from the first metal layer of the memory circuit.

30. The method of claim 29 wherein each diode comprises a vertically oriented diode.

31. The method of claim 29 wherein forming each two-terminal memory element comprises forming an antifuse coupled to a junction diode.

32. A method of forming a memory element comprising a diode, the method comprising:

forming an isolation region in a substrate;

forming a first conductor of a first conductivity type on the isolation region using a gate layer deposited on the substrate and employed as part of a gate electrode of a CMOS transistor for programming the memory element, the gate electrode being formed on the substrate;

forming an interlayer dielectric layer over the substrate;

forming a via opening in the interlayer dielectric layer to expose the first conductor, wherein the via opening extends from an upper surface of the interlayer dielectric layer to the first conductor;

filling the via opening with polysilicon;

doping an upper portion of the polysilicon filled via opening so as to form a polysilicon region of a second conductivity type; and

forming a second conductor above the upper portion of the polysilicon filled via opening directly on the upper surface of the interlayer dielectric layer, and wherein the memory element is formed between the first conductor and the second conductor.

33. The method of claim 32 wherein forming the first conductor comprises patterning the gate layer.

34. The method of claim 32 wherein forming the first conductor comprises forming an n+ polysilicon conductor.

35. The method of claim 32 wherein forming the second conductor comprises depositing a first metal layer on the substrate.

36. The method of claim 32 further comprising forming an antifuse layer on the polysilicon region of the second conductivity type prior to forming the second conductor.

37. A method of forming a memory circuit, the method comprising:

forming an isolation region in a substrate;

forming a plurality of memory elements by:

forming a plurality of first conductors of a first conductivity type on the isolation region using a gate layer deposited on the substrate and employed as part of a gate electrode of a CMOS transistor for programming the memory elements, the gate electrode being formed on the substrate;

forming an interlayer dielectric layer over the substrate;

forming a plurality of via openings in the interlayer dielectric layer to expose each first conductor, wherein each via opening extends from an upper surface of the interlayer dielectric to a corresponding one of the first conductors; and

forming a plurality of diodes by:

filling the via openings with polysilicon;

doping an upper portion of the polysilicon filled via openings so as to form a polysilicon region of a second conductivity type in each polysilicon filled via opening; and

forming a second conductor directly on the upper surface of the interlayer dielectric layer, and wherein each memory element is formed between a corresponding one of the first conductors and the second conductor.

38. The method of claim 37 wherein forming the first conductors comprises patterning the gate layer.

39. The method of claim 37 wherein forming the first conductors comprises forming n+ polysilicon conductors.

40. The method of claim 37 wherein forming the second conductor comprises depositing a first metal layer on the substrate.

41. The method of claim 37 further comprising forming an antifuse layer on each polysilicon region of the second conductivity type prior to forming the second conductor.

42. The method of claim 37 further comprising forming a salicide protection layer over the first conductors during at least a portion of the formation of the memory circuit.