Three dimensional NAND memory

1. A monolithic, three dimensional NAND string, comprising:

a first memory cell located over a second memory cell;

a select transistor;

a first word line of the first memory cell;

a second word line of the second memory cell;

a bit line;

a source line; and

a select gate line of the select transistor;

wherein:

the first and the second word lines are not parallel to the bit line;

the first and the second word lines extend parallel to at least one of the source line and the select gate line;

the NAND string is formed vertically over a substrate;

the select transistor is located in a trench in the substrate, the trench extending substantially parallel to the select gate line of the select transistor.

2. The NAND string of claim 1 , wherein:

the first memory cell is located in a first device level; and

the second memory cell is located in a second device level located on the select transistor and below the first device level.

3. The NAND string of claim 2 , wherein:

a semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell;

the semiconductor active region of the second memory cell is formed epitaxially on a semiconductor active region of the select transistor;

a first charge storage dielectric is located between the semiconductor active region of the first memory cell and the first word line; and

a second charge storage dielectric is located between the semiconductor active region of the second memory cell and the second word line.

4. The NAND string of claim 3 , wherein:

the semiconductor active region of the first memory cell comprises a first pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions;

the semiconductor active region of the second memory cell comprises a second pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions;

the semiconductor active region of the select transistor comprises a third pillar;

one second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar;

the first pillar is not aligned with the second pillar, such that the first pillar extends laterally past the second pillar; and

the second pillar is not aligned with the third pillar, such that the second pillar extends laterally past the third pillar.

5. The NAND string of claim 1 , wherein:

the first and the second word lines extend perpendicular to the bit line; and

the first and the second word lines extend parallel to both the source line and the select gate line.

6. The NAND string of claim 1 , wherein:

the first and the second word lines extend perpendicular to the bit line; and

the first and the second word lines extend parallel to the source line.

7. The NAND string of claim 1 , wherein:

the first and the second word lines extend perpendicular to the bit line; and

the first and the second word lines extend parallel to the select gate line.

8. A monolithic, three dimensional NAND string, comprising:

a first memory cell located over a second memory cell;

a select transistor;

a first word line of the first memory cell;

a second word line of the second memory cell;

a bit line;

a source line; and

a select gate line of the select transistor;

wherein:

the first and the second word lines are not parallel to the bit line;

the first and the second word lines extend parallel to at least one of the source line and the select gate line;

the NAND string is formed vertically over a substrate;

the select transistor is located on a substrate or in a trench in the substrate;

the first memory cell is located in a first device level;

the second memory cell is located in a second device level located on the select transistor and below the first device level;

a semiconductor active region of the first memory cell is formed epitaxially on a semiconductor active region of the second memory cell;

the semiconductor active region of the second memory cell is formed epitaxially on a semiconductor active region of the select transistor;

a first charge storage dielectric is located between the semiconductor active region of the first memory cell and the first word line;

a second charge storage dielectric is located between the semiconductor active region of the second memory cell and the second word line;

the semiconductor active region of the first memory cell comprises a first pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions;

the semiconductor active region of the second memory cell comprises a second pillar comprising a first conductivity type semiconductor region located between second conductivity type semiconductor regions;

the semiconductor active region of the select transistor comprises a third pillar;

one second conductivity type semiconductor region in the first pillar contacts one second conductivity type semiconductor region in the second pillar;

the first pillar is not aligned with the second pillar, such that the first pillar extends laterally past the second pillar; and

the second pillar is not aligned with the third pillar, such that the second pillar extends laterally past the third pillar.

9. The NAND string of claim 8 , wherein the first and the second word lines extend parallel to the source line.

10. The NAND string of claim 8 , wherein the first and the second word lines extend parallel to the select gate line.

11. The NAND string of claim 8 , wherein the first and the second word lines extend parallel to the source line and the select gate line.

12. The NAND string of claim 8 , wherein the select transistor is located on the substrate.

13. The NAND string of claim 8 , wherein the select transistor is located in the trench in the substrate.