Low power mode data preservation in secure ICs
Methods, apparatus and computer program products are provided for reducing power consumption in a device. One method includes identifying a plurality of addressable areas for storing data in a volatile memory element of a device and, responsive to a detection of a power condition in the device, enabling power to a first portion of the addressable areas and disabling power to a second portion.
1. A smartcard comprising:
a volatile memory including plurality of addressable areas for storing data; and
a controller, responsive to a lower power condition for enabling power to a first portion of the addressable areas and disabling power to a second portion where the controller dynamically allocates the portions over time including dynamically selecting a location of the first portion at each occurrence of a low power condition in accordance with a random selection, a round robin selection or a selection based on a plurality of predetermined configurations, dynamically selecting a new different location for the first portion when a lower power condition persists for longer than a predetermined period of time and moving data from the location to the new different location.
2. The smartcard of claim 1 where the addressable areas comprise a plurality of memory banks.
3. The smartcard of claim 2 further comprising a detector for detecting the lower power condition.
4. The smartcard of claim 2 where the controller dynamically determines which memory banks to power, and re-locates as necessary data that is required to be maintained during the lower power condition in powered banks of the volatile memory.
5. The smartcard of claim 4 where dynamically determining includes defining different portions for power at different points in time.
6. The smartcard of claim 4 where dynamically determining is controlled in software.
7. The smartcard of claim 6 where software moves data in response to a determination of which portion is powered.
8. The smartcard of claim 4 where dynamically includes randomly determining the first and second portions.
9. The smartcard of claim 1 where the controller includes an address scrambler operable to scramble addresses so that logical address associated with the memory map to different physical addresses in the memory.
10. A method comprising:
identifying a plurality of addressable areas for storing data in a volatile memory element of a device; and
responsive to a detection of a power condition in the device, enabling power to a first portion of the addressable areas and disabling power to a second portion including dynamically allocating the portions over time including dynamically selecting a location of the first portion at each occurrence of a low power condition in accordance with a random selection, a round robin selection or a selection based on a plurality of predetermined configurations, dynamically selecting a new different location for the first portion when a lower power condition persists for longer than a predetermined period of time and moving data from the location to the new different location.
11. The method of claim 10 where the power condition is a low power condition and where the method further comprises detecting the low power condition.
12. The method of claim 10 where the addressable areas comprise a plurality of memory banks.
13. The method of claim 12 further comprising dynamically determining which memory banks to power, and re-locating as necessary data that is required to be maintained during the power condition in powered banks of the volatile memory.
14. The method of claim 13 where dynamically determining includes defining different portions for power of the volatile memory at different points in time.
15. The method of claim 13 where dynamically determining is controlled in software.
16. The method of claim 13 where dynamically determining includes randomly determining the first and second portions.
17. The method of claim 10 further comprising scrambling addresses so that logical address associated with the volatile memory element map to different physical addresses in the volatile memory element.
18. A circuit comprising:
a volatile memory including plurality of addressable areas for storing data; and
a controller, responsive to a lower power condition for enabling power to a first portion of the addressable areas and disabling power to a second portion where the controller dynamically allocates the portions over time including dynamically selecting a location of the first portion at each occurrence of a low power condition in accordance with a random selection, a round robin selection or a selection based on a plurality of predetermined configurations where the plurality of predetermined configurations are determined prior to a start of a low power condition.
19. The circuit of claim 18 where the addressable areas comprise a plurality of memory banks and a detector for detecting the lower power condition.
20. The circuit of claim 19 where the controller dynamically determines which memory banks to power, and re-locates as necessary data that is required to be maintained during the lower power condition in powered banks of the volatile memory.
21. The circuit of claim 20 where dynamically determining includes defining different portions for power at different points in time.
22. The circuit of claim 20 where dynamically includes randomly determining the first and second portions.
23. The circuit of claim 18 where the controller includes an address scrambler operable to scramble addresses so that logical address associated with the memory map to different physical addresses in the memory.